LC_CTRL/VOLATILE_UNLOCK_DISABLED Simulation Results

Wednesday June 05 2024 22:14:46 UTC

GitHub Revision: b29ffbb03c

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 104714960319679935410420483500971829136303708457300037460974663680452494898918

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	7.810s	448.255us	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.210s	16.195us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.180s	18.287us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	2.430s	273.488us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	1.250s	372.081us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	1.680s	85.745us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.180s	18.287us	20	20	100.00
		lc_ctrl_csr_aliasing	1.250s	372.081us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	9.960s	362.654us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	25.800s	1.513ms	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	0.990s	37.733us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	4.500s	98.377us	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	40.840s	375.204us	50	50	100.00
V2	lc_errors	lc_ctrl_errors	23.010s	589.921us	50	50	100.00
V2	security_escalation	lc_ctrl_state_failure	40.840s	375.204us	50	50	100.00
		lc_ctrl_prog_failure	4.500s	98.377us	50	50	100.00
		lc_ctrl_errors	23.010s	589.921us	50	50	100.00
		lc_ctrl_security_escalation	15.650s	666.235us	50	50	100.00
		lc_ctrl_jtag_state_failure	2.525m	19.626ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	13.890s	460.997us	20	20	100.00
		lc_ctrl_jtag_errors	2.300m	10.800ms	20	20	100.00
V2	jtag_access	lc_ctrl_jtag_smoke	15.340s	593.289us	20	20	100.00
		lc_ctrl_jtag_state_post_trans	33.170s	3.624ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	13.890s	460.997us	20	20	100.00
		lc_ctrl_jtag_errors	2.300m	10.800ms	20	20	100.00
		lc_ctrl_jtag_access	23.520s	1.968ms	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	41.370s	1.454ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	3.130s	138.930us	10	10	100.00
		lc_ctrl_jtag_csr_rw	4.360s	1.418ms	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	21.950s	4.498ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	22.210s	4.794ms	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	1.900s	183.081us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	3.700s	101.882us	10	10	100.00
		lc_ctrl_jtag_alert_test	2.180s	680.494us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	11.600s	4.246ms	10	10	100.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.210s	86.980us	50	50	100.00
V2	stress_all	lc_ctrl_stress_all	6.099m	12.884ms	49	50	98.00
V2	alert_test	lc_ctrl_alert_test	1.410s	129.161us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	4.660s	116.743us	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	4.660s	116.743us	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.210s	16.195us	5	5	100.00
		lc_ctrl_csr_rw	1.180s	18.287us	20	20	100.00
		lc_ctrl_csr_aliasing	1.250s	372.081us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.850s	77.906us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.210s	16.195us	5	5	100.00
		lc_ctrl_csr_rw	1.180s	18.287us	20	20	100.00
		lc_ctrl_csr_aliasing	1.250s	372.081us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.850s	77.906us	20	20	100.00
V2		TOTAL			699	700	99.86
V2S	tl_intg_err	lc_ctrl_sec_cm	46.220s	474.070us	5	5	100.00
		lc_ctrl_tl_intg_err	3.910s	426.761us	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	3.910s	426.761us	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	25.800s	1.513ms	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	40.840s	375.204us	50	50	100.00
		lc_ctrl_sec_cm	46.220s	474.070us	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	40.840s	375.204us	50	50	100.00
		lc_ctrl_sec_cm	46.220s	474.070us	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	40.840s	375.204us	50	50	100.00
		lc_ctrl_sec_cm	46.220s	474.070us	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	40.840s	375.204us	50	50	100.00
		lc_ctrl_sec_cm	46.220s	474.070us	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	40.840s	375.204us	50	50	100.00
		lc_ctrl_sec_cm	46.220s	474.070us	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	40.840s	375.204us	50	50	100.00
		lc_ctrl_sec_cm	46.220s	474.070us	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	40.840s	375.204us	50	50	100.00
		lc_ctrl_sec_cm	46.220s	474.070us	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	40.840s	375.204us	50	50	100.00
		lc_ctrl_sec_cm	46.220s	474.070us	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	15.650s	666.235us	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	9.960s	362.654us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	33.170s	3.624ms	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	28.870s	1.866ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	28.870s	1.866ms	50	50	100.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	29.360s	4.807ms	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	15.710s	4.244ms	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	15.710s	4.244ms	50	50	100.00
V2S		TOTAL			175	175	100.00
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	2.326h	385.480ms	18	50	36.00
V3		TOTAL			18	50	36.00
		TOTAL			997	1030	96.80

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	26	96.30
V2S	5	5	5	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.92	97.82	95.93	93.31	97.62	98.52	98.76	96.47

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:828) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 26 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 26 failures.

    • 2.lc_ctrl_stress_all_with_rand_reset.58520932919457043021518558540860168037854083312861333202024136274133265238777
      Line 21839, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/2.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 37398179160 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10007 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 37398179160 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 4.lc_ctrl_stress_all_with_rand_reset.5662300513869735607792611089060395023705866670855865075618836570841767902470
      Line 26965, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/4.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 468615302627 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 468615302627 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 24 more failures.

• UVM_ERROR (cip_base_vseq.sv:554) [lc_ctrl_common_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_state_error fired unexpectedly! has 2 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 2 failures.

    • 1.lc_ctrl_stress_all_with_rand_reset.3100163367097290442733644528449084234405779363900089254394139327798779951380
      Line 20903, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/1.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 33353584198 ps: (cip_base_vseq.sv:554) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
        UVM_INFO @ 33353584198 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 29.lc_ctrl_stress_all_with_rand_reset.4033054175630630967661757976198114379100845466407275489488136645052714761910
      Line 37863, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/29.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 171426967272 ps: (cip_base_vseq.sv:554) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
        UVM_INFO @ 171426967272 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_scoreboard.sv:301) scoreboard [scoreboard] alert fatal_prog_error did not trigger max_delay:* has 2 failures:

  • Test lc_ctrl_stress_all has 1 failures.

    • 7.lc_ctrl_stress_all.79277356385042836503382359256243896783338114516721336107902205554984800927144
      Line 6234, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/7.lc_ctrl_stress_all/latest/run.log

        UVM_ERROR @ 7796975311 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 7796975311 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 42.lc_ctrl_stress_all_with_rand_reset.95180879979197848931513086927772622204045867905151880742643759390553826194958
      Line 30458, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/42.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 17315667180 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 17315667180 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Error-[CNST-STOF] Constraint solver timeout failure has 2 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 2 failures.

    • 18.lc_ctrl_stress_all_with_rand_reset.111974974683587025895291718156577028385687847849712609574305288271154126380263
      Line 52537, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/18.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        Error-[CNST-STOF] Constraint solver timeout failure
        ../src/lowrisc_dv_sec_cm_0/prim_sparse_fsm_flop_if.sv, 43
          Exceeded cpu time limit during solve.
          Please use the run-time switch +ntb_solver_cpu_limit to increase the cpu
          limit.  The default cpu limit is 1000 seconds per partition.
      

    • 26.lc_ctrl_stress_all_with_rand_reset.85057153595533887006241308025087625605058475710494864932056873746662776210811
      Line 39863, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/26.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        Error-[CNST-STOF] Constraint solver timeout failure
        ../src/lowrisc_dv_sec_cm_0/prim_sparse_fsm_flop_if.sv, 43
          Exceeded cpu time limit during solve.
          Please use the run-time switch +ntb_solver_cpu_limit to increase the cpu
          limit.  The default cpu limit is 1000 seconds per partition.
      

• UVM_ERROR (cip_base_vseq.sv:554) [lc_ctrl_smoke_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_prog_error fired unexpectedly! has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 39.lc_ctrl_stress_all_with_rand_reset.72189759253775998068334306318248620205189704426997710256345349474630436976369
      Line 3745, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/39.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 921386422 ps: (cip_base_vseq.sv:554) [uvm_test_top.env.virtual_sequencer.lc_ctrl_smoke_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_prog_error fired unexpectedly!
        UVM_INFO @ 921386422 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

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