LC_CTRL/VOLATILE_UNLOCK_DISABLED Simulation Results

Thursday June 06 2024 19:04:47 UTC

GitHub Revision: 32d52b8d41

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 59908589074363629542901507660786833114562191729708937078847065421241135561861

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	5.680s	289.697us	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.200s	27.326us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.160s	17.823us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	2.850s	383.090us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	1.540s	335.127us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	2.420s	30.549us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.160s	17.823us	20	20	100.00
		lc_ctrl_csr_aliasing	1.540s	335.127us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	10.850s	366.384us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	22.000s	758.070us	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	0.940s	10.560us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	6.100s	612.984us	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	37.590s	749.303us	50	50	100.00
V2	lc_errors	lc_ctrl_errors	20.860s	489.189us	50	50	100.00
V2	security_escalation	lc_ctrl_state_failure	37.590s	749.303us	50	50	100.00
		lc_ctrl_prog_failure	6.100s	612.984us	50	50	100.00
		lc_ctrl_errors	20.860s	489.189us	50	50	100.00
		lc_ctrl_security_escalation	13.780s	387.067us	50	50	100.00
		lc_ctrl_jtag_state_failure	1.415m	9.795ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	17.460s	2.678ms	20	20	100.00
		lc_ctrl_jtag_errors	2.040m	4.795ms	20	20	100.00
V2	jtag_access	lc_ctrl_jtag_smoke	16.370s	630.563us	20	20	100.00
		lc_ctrl_jtag_state_post_trans	30.790s	1.092ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	17.460s	2.678ms	20	20	100.00
		lc_ctrl_jtag_errors	2.040m	4.795ms	20	20	100.00
		lc_ctrl_jtag_access	28.480s	1.213ms	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	35.440s	1.179ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	6.580s	1.607ms	10	10	100.00
		lc_ctrl_jtag_csr_rw	3.450s	116.033us	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	39.700s	3.951ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	24.560s	7.518ms	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	1.510s	22.569us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	2.710s	339.418us	10	10	100.00
		lc_ctrl_jtag_alert_test	1.260s	277.011us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	15.340s	961.055us	10	10	100.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.170s	213.215us	49	50	98.00
V2	stress_all	lc_ctrl_stress_all	11.322m	86.038ms	50	50	100.00
V2	alert_test	lc_ctrl_alert_test	1.440s	89.850us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	3.850s	134.169us	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	3.850s	134.169us	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.200s	27.326us	5	5	100.00
		lc_ctrl_csr_rw	1.160s	17.823us	20	20	100.00
		lc_ctrl_csr_aliasing	1.540s	335.127us	5	5	100.00
		lc_ctrl_same_csr_outstanding	2.040s	97.349us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.200s	27.326us	5	5	100.00
		lc_ctrl_csr_rw	1.160s	17.823us	20	20	100.00
		lc_ctrl_csr_aliasing	1.540s	335.127us	5	5	100.00
		lc_ctrl_same_csr_outstanding	2.040s	97.349us	20	20	100.00
V2		TOTAL			699	700	99.86
V2S	tl_intg_err	lc_ctrl_sec_cm	35.580s	234.871us	5	5	100.00
		lc_ctrl_tl_intg_err	4.340s	518.609us	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	4.340s	518.609us	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	22.000s	758.070us	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	37.590s	749.303us	50	50	100.00
		lc_ctrl_sec_cm	35.580s	234.871us	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	37.590s	749.303us	50	50	100.00
		lc_ctrl_sec_cm	35.580s	234.871us	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	37.590s	749.303us	50	50	100.00
		lc_ctrl_sec_cm	35.580s	234.871us	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	37.590s	749.303us	50	50	100.00
		lc_ctrl_sec_cm	35.580s	234.871us	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	37.590s	749.303us	50	50	100.00
		lc_ctrl_sec_cm	35.580s	234.871us	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	37.590s	749.303us	50	50	100.00
		lc_ctrl_sec_cm	35.580s	234.871us	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	37.590s	749.303us	50	50	100.00
		lc_ctrl_sec_cm	35.580s	234.871us	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	37.590s	749.303us	50	50	100.00
		lc_ctrl_sec_cm	35.580s	234.871us	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	13.780s	387.067us	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	10.850s	366.384us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	30.790s	1.092ms	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	22.180s	3.460ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	22.180s	3.460ms	50	50	100.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	21.370s	607.971us	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	15.580s	831.357us	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	15.580s	831.357us	50	50	100.00
V2S		TOTAL			175	175	100.00
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	1.629h	285.404ms	28	50	56.00
V3		TOTAL			28	50	56.00
		TOTAL			1007	1030	97.77

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	26	96.30
V2S	5	5	5	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.92	97.82	96.03	93.31	97.62	98.52	99.00	96.11

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:828) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 19 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 19 failures.

    • 6.lc_ctrl_stress_all_with_rand_reset.108322388896783357196675149618979649589097398204097207197181544699202751058213
      Line 22385, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/6.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 99566657351 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 99566657351 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 11.lc_ctrl_stress_all_with_rand_reset.68032832728044989519345033904188731685544560593134427468476478936026685722856
      Line 46794, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/11.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 70419891722 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 70419891722 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 17 more failures.

• Error-[CNST-STOF] Constraint solver timeout failure has 2 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 2 failures.

    • 13.lc_ctrl_stress_all_with_rand_reset.32224409162658683218867770069902712152101594792991323872844002906405719963009
      Line 52665, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/13.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        Error-[CNST-STOF] Constraint solver timeout failure
        ../src/lowrisc_dv_sec_cm_0/prim_sparse_fsm_flop_if.sv, 43
          Exceeded cpu time limit during solve.
          Please use the run-time switch +ntb_solver_cpu_limit to increase the cpu
          limit.  The default cpu limit is 1000 seconds per partition.
      

    • 28.lc_ctrl_stress_all_with_rand_reset.68340571578787395509817158399004599992370985577795309530473123047589669667839
      Line 37395, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/28.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        Error-[CNST-STOF] Constraint solver timeout failure
        ../src/lowrisc_dv_sec_cm_0/prim_sparse_fsm_flop_if.sv, 43
          Exceeded cpu time limit during solve.
          Please use the run-time switch +ntb_solver_cpu_limit to increase the cpu
          limit.  The default cpu limit is 1000 seconds per partition.
      

• UVM_ERROR (cip_base_scoreboard.sv:301) scoreboard [scoreboard] alert fatal_prog_error did not trigger max_delay:* has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 35.lc_ctrl_stress_all_with_rand_reset.22274289102419480023414387060566443489367125310456363697585781857560558190770
      Line 17384, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/35.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 16068062867 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 16068062867 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (csr_utils_pkg.sv:576) [csr_utils::csr_spinwait] timeout lc_ctrl_reg_block.status.token_error (addr=*) == * has 1 failures:

  • Test lc_ctrl_volatile_unlock_smoke has 1 failures.

    • 40.lc_ctrl_volatile_unlock_smoke.47281125723857473526119489747792248169898825353918135899144635259341036554264
      Line 322, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/40.lc_ctrl_volatile_unlock_smoke/latest/run.log

        UVM_FATAL @ 143220136 ps: (csr_utils_pkg.sv:576) [csr_utils::csr_spinwait] timeout lc_ctrl_reg_block.status.token_error (addr=0x78aed804) == 0x1
        UVM_INFO @ 143220136 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

• Latest
• 2024.06.06_10.58.47
• 2024.06.05_03.50.58
• 2024.06.03_06.54.07
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