LC_CTRL/VOLATILE_UNLOCK_DISABLED Simulation Results

Saturday June 08 2024 00:41:57 UTC

GitHub Revision: 302b24f3c6

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 32491226968592963393132943636196950930602503490106290691157604759716956925599

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	6.320s	210.474us	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.040s	18.897us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.140s	31.669us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	1.900s	171.697us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	1.250s	126.713us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	1.940s	96.872us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.140s	31.669us	20	20	100.00
		lc_ctrl_csr_aliasing	1.250s	126.713us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	10.820s	196.557us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	17.340s	2.779ms	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	0.990s	12.057us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	6.150s	347.219us	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	40.110s	321.884us	50	50	100.00
V2	lc_errors	lc_ctrl_errors	18.970s	414.427us	50	50	100.00
V2	security_escalation	lc_ctrl_state_failure	40.110s	321.884us	50	50	100.00
		lc_ctrl_prog_failure	6.150s	347.219us	50	50	100.00
		lc_ctrl_errors	18.970s	414.427us	50	50	100.00
		lc_ctrl_security_escalation	16.350s	7.622ms	50	50	100.00
		lc_ctrl_jtag_state_failure	2.613m	19.093ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	12.810s	2.832ms	20	20	100.00
		lc_ctrl_jtag_errors	1.423m	21.041ms	20	20	100.00
V2	jtag_access	lc_ctrl_jtag_smoke	19.190s	2.974ms	20	20	100.00
		lc_ctrl_jtag_state_post_trans	36.440s	1.519ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	12.810s	2.832ms	20	20	100.00
		lc_ctrl_jtag_errors	1.423m	21.041ms	20	20	100.00
		lc_ctrl_jtag_access	27.250s	1.162ms	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	37.810s	2.646ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	4.050s	1.341ms	10	10	100.00
		lc_ctrl_jtag_csr_rw	2.420s	76.629us	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	15.430s	7.784ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	26.060s	2.192ms	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	1.470s	20.647us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	5.910s	884.865us	10	10	100.00
		lc_ctrl_jtag_alert_test	2.670s	562.427us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	29.530s	2.934ms	10	10	100.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.170s	132.483us	50	50	100.00
V2	stress_all	lc_ctrl_stress_all	9.504m	142.376ms	49	50	98.00
V2	alert_test	lc_ctrl_alert_test	1.530s	38.275us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	4.830s	258.852us	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	4.830s	258.852us	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.040s	18.897us	5	5	100.00
		lc_ctrl_csr_rw	1.140s	31.669us	20	20	100.00
		lc_ctrl_csr_aliasing	1.250s	126.713us	5	5	100.00
		lc_ctrl_same_csr_outstanding	2.010s	94.007us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.040s	18.897us	5	5	100.00
		lc_ctrl_csr_rw	1.140s	31.669us	20	20	100.00
		lc_ctrl_csr_aliasing	1.250s	126.713us	5	5	100.00
		lc_ctrl_same_csr_outstanding	2.010s	94.007us	20	20	100.00
V2		TOTAL			699	700	99.86
V2S	tl_intg_err	lc_ctrl_sec_cm	40.900s	1.104ms	5	5	100.00
		lc_ctrl_tl_intg_err	4.730s	590.029us	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	4.730s	590.029us	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	17.340s	2.779ms	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	40.110s	321.884us	50	50	100.00
		lc_ctrl_sec_cm	40.900s	1.104ms	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	40.110s	321.884us	50	50	100.00
		lc_ctrl_sec_cm	40.900s	1.104ms	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	40.110s	321.884us	50	50	100.00
		lc_ctrl_sec_cm	40.900s	1.104ms	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	40.110s	321.884us	50	50	100.00
		lc_ctrl_sec_cm	40.900s	1.104ms	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	40.110s	321.884us	50	50	100.00
		lc_ctrl_sec_cm	40.900s	1.104ms	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	40.110s	321.884us	50	50	100.00
		lc_ctrl_sec_cm	40.900s	1.104ms	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	40.110s	321.884us	50	50	100.00
		lc_ctrl_sec_cm	40.900s	1.104ms	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	40.110s	321.884us	50	50	100.00
		lc_ctrl_sec_cm	40.900s	1.104ms	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	16.350s	7.622ms	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	10.820s	196.557us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	36.440s	1.519ms	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	20.400s	3.431ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	20.400s	3.431ms	50	50	100.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	19.380s	2.171ms	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	14.450s	3.397ms	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	14.450s	3.397ms	50	50	100.00
V2S		TOTAL			175	175	100.00
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	1.150h	20.190ms	15	50	30.00
V3		TOTAL			15	50	30.00
		TOTAL			994	1030	96.50

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	26	96.30
V2S	5	5	5	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.83	97.82	95.84	93.34	97.62	98.52	98.76	95.94

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:828) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 26 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 26 failures.

    • 0.lc_ctrl_stress_all_with_rand_reset.87665921181776980041383044845826762076675320534586750830344081782463328487505
      Line 22615, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/0.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 15680492241 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 15680492241 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 1.lc_ctrl_stress_all_with_rand_reset.38686462733657054632968203587421104451623435177544342443874910515590135180172
      Line 40744, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/1.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 250308688036 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 250308688036 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 24 more failures.

• UVM_ERROR (cip_base_vseq.sv:554) [lc_ctrl_common_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_state_error fired unexpectedly! has 3 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 3 failures.

    • 16.lc_ctrl_stress_all_with_rand_reset.66968077291661551738513927378112918220643890794544502465094858955697702947977
      Line 18821, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/16.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 14217241854 ps: (cip_base_vseq.sv:554) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
        UVM_INFO @ 14217241854 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 24.lc_ctrl_stress_all_with_rand_reset.93536621839191212973774536473806156687090759329682435451579452175741995521848
      Line 25751, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/24.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 23959336645 ps: (cip_base_vseq.sv:554) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
        UVM_INFO @ 23959336645 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 1 more failures.

• UVM_ERROR (cip_base_scoreboard.sv:301) scoreboard [scoreboard] alert fatal_prog_error did not trigger max_delay:* has 2 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 3.lc_ctrl_stress_all_with_rand_reset.12015608393468767739923830327205896805309205675667606694049516089765753194527
      Line 40971, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/3.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 98996686825 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 98996686825 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test lc_ctrl_stress_all has 1 failures.

    • 32.lc_ctrl_stress_all.102231195592880709544802762746943886873768525461062295069494980055803574510167
      Line 2176, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/32.lc_ctrl_stress_all/latest/run.log

        UVM_ERROR @ 3924112725 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 3924112725 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Error-[CNST-STOF] Constraint solver timeout failure has 2 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 2 failures.

    • 18.lc_ctrl_stress_all_with_rand_reset.21278926354613382176393563468069436045009518546674942892580495790101027334420
      Line 56243, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/18.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        Error-[CNST-STOF] Constraint solver timeout failure
        ../src/lowrisc_dv_sec_cm_0/prim_sparse_fsm_flop_if.sv, 43
          Exceeded cpu time limit during solve.
          Please use the run-time switch +ntb_solver_cpu_limit to increase the cpu
          limit.  The default cpu limit is 1000 seconds per partition.
      

    • 21.lc_ctrl_stress_all_with_rand_reset.16272056811234743869576346954462272180685991191698020195147597642359041117905
      Line 32402, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/21.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        Error-[CNST-STOF] Constraint solver timeout failure
        ../src/lowrisc_dv_sec_cm_0/prim_sparse_fsm_flop_if.sv, 43
          Exceeded cpu time limit during solve.
          Please use the run-time switch +ntb_solver_cpu_limit to increase the cpu
          limit.  The default cpu limit is 1000 seconds per partition.
      

• UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (* [*] vs * [*]) has 2 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 2 failures.

    • 19.lc_ctrl_stress_all_with_rand_reset.62549832026433066979306477901797772905115802941443635944035263422891054598449
      Line 9830, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/19.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 5770124774 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 5770124774 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 30.lc_ctrl_stress_all_with_rand_reset.81229769565687017862581936774362196846924459854144807451669618204539139293379
      Line 48983, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/30.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 24734519097 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 24734519097 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:554) [lc_ctrl_smoke_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_prog_error fired unexpectedly! has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 4.lc_ctrl_stress_all_with_rand_reset.28447320089445686018490294310305635768633400022237955713562426945913191631612
      Line 29753, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/4.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 27921302543 ps: (cip_base_vseq.sv:554) [uvm_test_top.env.virtual_sequencer.lc_ctrl_smoke_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_prog_error fired unexpectedly!
        UVM_INFO @ 27921302543 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

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