LC_CTRL/VOLATILE_UNLOCK_DISABLED Simulation Results

Sunday June 09 2024 19:02:32 UTC

GitHub Revision: f92a5ee77b

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 74888572473032497941251936200792687439223302665780333354656685678472336958420

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	5.670s	488.254us	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.210s	16.752us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.140s	18.267us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	1.990s	50.357us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	1.400s	139.161us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	2.460s	85.104us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.140s	18.267us	20	20	100.00
		lc_ctrl_csr_aliasing	1.400s	139.161us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	9.190s	285.443us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	17.820s	561.206us	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	0.940s	24.930us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	5.020s	383.701us	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	39.280s	1.374ms	50	50	100.00
V2	lc_errors	lc_ctrl_errors	25.960s	4.625ms	50	50	100.00
V2	security_escalation	lc_ctrl_state_failure	39.280s	1.374ms	50	50	100.00
		lc_ctrl_prog_failure	5.020s	383.701us	50	50	100.00
		lc_ctrl_errors	25.960s	4.625ms	50	50	100.00
		lc_ctrl_security_escalation	15.220s	416.958us	50	50	100.00
		lc_ctrl_jtag_state_failure	2.240m	4.451ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	17.380s	2.535ms	20	20	100.00
		lc_ctrl_jtag_errors	1.203m	22.127ms	20	20	100.00
V2	jtag_access	lc_ctrl_jtag_smoke	20.980s	3.466ms	20	20	100.00
		lc_ctrl_jtag_state_post_trans	39.460s	1.248ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	17.380s	2.535ms	20	20	100.00
		lc_ctrl_jtag_errors	1.203m	22.127ms	20	20	100.00
		lc_ctrl_jtag_access	25.730s	4.509ms	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	31.150s	9.954ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	6.020s	269.635us	10	10	100.00
		lc_ctrl_jtag_csr_rw	3.470s	128.793us	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	27.250s	2.120ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	14.340s	1.159ms	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	1.810s	83.576us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	6.490s	302.910us	10	10	100.00
		lc_ctrl_jtag_alert_test	2.380s	249.632us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	29.550s	5.445ms	10	10	100.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.250s	39.486us	50	50	100.00
V2	stress_all	lc_ctrl_stress_all	6.178m	53.769ms	50	50	100.00
V2	alert_test	lc_ctrl_alert_test	1.370s	26.790us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	4.820s	156.849us	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	4.820s	156.849us	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.210s	16.752us	5	5	100.00
		lc_ctrl_csr_rw	1.140s	18.267us	20	20	100.00
		lc_ctrl_csr_aliasing	1.400s	139.161us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.880s	218.805us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.210s	16.752us	5	5	100.00
		lc_ctrl_csr_rw	1.140s	18.267us	20	20	100.00
		lc_ctrl_csr_aliasing	1.400s	139.161us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.880s	218.805us	20	20	100.00
V2		TOTAL			700	700	100.00
V2S	tl_intg_err	lc_ctrl_sec_cm	35.030s	275.599us	5	5	100.00
		lc_ctrl_tl_intg_err	4.230s	115.396us	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	4.230s	115.396us	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	17.820s	561.206us	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	39.280s	1.374ms	50	50	100.00
		lc_ctrl_sec_cm	35.030s	275.599us	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	39.280s	1.374ms	50	50	100.00
		lc_ctrl_sec_cm	35.030s	275.599us	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	39.280s	1.374ms	50	50	100.00
		lc_ctrl_sec_cm	35.030s	275.599us	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	39.280s	1.374ms	50	50	100.00
		lc_ctrl_sec_cm	35.030s	275.599us	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	39.280s	1.374ms	50	50	100.00
		lc_ctrl_sec_cm	35.030s	275.599us	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	39.280s	1.374ms	50	50	100.00
		lc_ctrl_sec_cm	35.030s	275.599us	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	39.280s	1.374ms	50	50	100.00
		lc_ctrl_sec_cm	35.030s	275.599us	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	39.280s	1.374ms	50	50	100.00
		lc_ctrl_sec_cm	35.030s	275.599us	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	15.220s	416.958us	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	9.190s	285.443us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	39.460s	1.248ms	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	24.130s	812.304us	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	24.130s	812.304us	50	50	100.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	23.950s	3.596ms	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	21.260s	625.447us	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	21.260s	625.447us	50	50	100.00
V2S		TOTAL			175	175	100.00
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	43.145m	47.033ms	20	50	40.00
V3		TOTAL			20	50	40.00
		TOTAL			1000	1030	97.09

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	27	100.00
V2S	5	5	5	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.25	97.82	96.03	93.34	100.00	98.52	98.76	96.29

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:828) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 23 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 23 failures.

    • 1.lc_ctrl_stress_all_with_rand_reset.7897274783465139728469174068582105889108369245664610698775203008013771626901
      Line 28412, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/1.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 21817687830 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 21817687830 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 3.lc_ctrl_stress_all_with_rand_reset.89639830265717656886053834324314851237870034217212722011735652175533549707579
      Line 25985, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/3.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 49595717039 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 49595717039 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 21 more failures.

• UVM_ERROR (cip_base_scoreboard.sv:301) scoreboard [scoreboard] alert fatal_prog_error did not trigger max_delay:* has 3 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 3 failures.

    • 28.lc_ctrl_stress_all_with_rand_reset.80474563975406975043513860388311812124883137889234518654488525437807062020016
      Line 45426, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/28.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 137252119664 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 137252119664 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 34.lc_ctrl_stress_all_with_rand_reset.9420896633347481341549238711678265003758840295972413623588650050687920978083
      Line 2290, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/34.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 4925488118 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 4925488118 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 1 more failures.

• Error-[CNST-STOF] Constraint solver timeout failure has 2 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 2 failures.

    • 12.lc_ctrl_stress_all_with_rand_reset.39973157550274520547182161867331028358092103582754893558471522539049137904712
      Line 42080, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/12.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        Error-[CNST-STOF] Constraint solver timeout failure
        ../src/lowrisc_dv_sec_cm_0/prim_sparse_fsm_flop_if.sv, 43
          Exceeded cpu time limit during solve.
          Please use the run-time switch +ntb_solver_cpu_limit to increase the cpu
          limit.  The default cpu limit is 1000 seconds per partition.
      

    • 16.lc_ctrl_stress_all_with_rand_reset.60927659684208694622385066682680008444538527410308499443189916224671907633608
      Line 39904, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/16.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        Error-[CNST-STOF] Constraint solver timeout failure
        ../src/lowrisc_dv_sec_cm_0/prim_sparse_fsm_flop_if.sv, 43
          Exceeded cpu time limit during solve.
          Please use the run-time switch +ntb_solver_cpu_limit to increase the cpu
          limit.  The default cpu limit is 1000 seconds per partition.
      

• UVM_ERROR (cip_base_vseq.sv:554) [lc_ctrl_common_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_state_error fired unexpectedly! has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 18.lc_ctrl_stress_all_with_rand_reset.78928873154171614953850257725729399797087515251001058648954732345032167186456
      Line 4202, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/18.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 35122911618 ps: (cip_base_vseq.sv:554) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
        UVM_INFO @ 35122911618 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (lc_ctrl_errors_vseq.sv:769) [lc_ctrl_lc_errors_vseq] Check failed otp_error_act == otp_error_exp (* [*] vs * [*]) has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 40.lc_ctrl_stress_all_with_rand_reset.53035232190401369865857296802667372774703170225083375011697273184534872287865
      Line 19370, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/40.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 18400211908 ps: (lc_ctrl_errors_vseq.sv:769) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed otp_error_act == otp_error_exp (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 18400211908 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

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