LC_CTRL/VOLATILE_UNLOCK_DISABLED Simulation Results

Monday June 10 2024 23:28:43 UTC

GitHub Revision: a8c9c17a8c

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 72227341233107832543509484606850665418885932500709631655793413524197290927900

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	8.710s	219.858us	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.160s	17.176us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.170s	18.373us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	2.610s	257.112us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	1.430s	29.012us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	2.150s	93.423us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.170s	18.373us	20	20	100.00
		lc_ctrl_csr_aliasing	1.430s	29.012us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	10.920s	542.619us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	22.270s	574.430us	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	1.030s	13.169us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	4.150s	279.781us	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	33.070s	1.207ms	50	50	100.00
V2	lc_errors	lc_ctrl_errors	20.080s	4.653ms	49	50	98.00
V2	security_escalation	lc_ctrl_state_failure	33.070s	1.207ms	50	50	100.00
		lc_ctrl_prog_failure	4.150s	279.781us	50	50	100.00
		lc_ctrl_errors	20.080s	4.653ms	49	50	98.00
		lc_ctrl_security_escalation	15.230s	7.314ms	50	50	100.00
		lc_ctrl_jtag_state_failure	1.537m	7.316ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	25.730s	993.239us	20	20	100.00
		lc_ctrl_jtag_errors	1.392m	13.193ms	20	20	100.00
V2	jtag_access	lc_ctrl_jtag_smoke	13.240s	1.079ms	20	20	100.00
		lc_ctrl_jtag_state_post_trans	29.350s	838.402us	20	20	100.00
		lc_ctrl_jtag_prog_failure	25.730s	993.239us	20	20	100.00
		lc_ctrl_jtag_errors	1.392m	13.193ms	20	20	100.00
		lc_ctrl_jtag_access	23.710s	1.071ms	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	50.010s	1.858ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	4.570s	164.344us	10	10	100.00
		lc_ctrl_jtag_csr_rw	3.090s	103.329us	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	39.080s	4.818ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	17.360s	4.493ms	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	1.520s	274.068us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	3.710s	139.683us	10	10	100.00
		lc_ctrl_jtag_alert_test	2.640s	184.458us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	14.570s	599.582us	10	10	100.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.250s	99.609us	50	50	100.00
V2	stress_all	lc_ctrl_stress_all	9.595m	22.369ms	50	50	100.00
V2	alert_test	lc_ctrl_alert_test	1.290s	106.165us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	5.550s	136.509us	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	5.550s	136.509us	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.160s	17.176us	5	5	100.00
		lc_ctrl_csr_rw	1.170s	18.373us	20	20	100.00
		lc_ctrl_csr_aliasing	1.430s	29.012us	5	5	100.00
		lc_ctrl_same_csr_outstanding	2.090s	505.479us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.160s	17.176us	5	5	100.00
		lc_ctrl_csr_rw	1.170s	18.373us	20	20	100.00
		lc_ctrl_csr_aliasing	1.430s	29.012us	5	5	100.00
		lc_ctrl_same_csr_outstanding	2.090s	505.479us	20	20	100.00
V2		TOTAL			699	700	99.86
V2S	tl_intg_err	lc_ctrl_sec_cm	40.430s	868.647us	5	5	100.00
		lc_ctrl_tl_intg_err	4.340s	422.698us	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	4.340s	422.698us	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	22.270s	574.430us	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	33.070s	1.207ms	50	50	100.00
		lc_ctrl_sec_cm	40.430s	868.647us	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	33.070s	1.207ms	50	50	100.00
		lc_ctrl_sec_cm	40.430s	868.647us	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	33.070s	1.207ms	50	50	100.00
		lc_ctrl_sec_cm	40.430s	868.647us	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	33.070s	1.207ms	50	50	100.00
		lc_ctrl_sec_cm	40.430s	868.647us	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	33.070s	1.207ms	50	50	100.00
		lc_ctrl_sec_cm	40.430s	868.647us	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	33.070s	1.207ms	50	50	100.00
		lc_ctrl_sec_cm	40.430s	868.647us	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	33.070s	1.207ms	50	50	100.00
		lc_ctrl_sec_cm	40.430s	868.647us	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	33.070s	1.207ms	50	50	100.00
		lc_ctrl_sec_cm	40.430s	868.647us	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	15.230s	7.314ms	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	10.920s	542.619us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	29.350s	838.402us	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	24.120s	3.928ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	24.120s	3.928ms	50	50	100.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	24.750s	5.417ms	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	23.750s	1.729ms	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	23.750s	1.729ms	50	50	100.00
V2S		TOTAL			175	175	100.00
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	31.578m	220.808ms	22	50	44.00
V3		TOTAL			22	50	44.00
		TOTAL			1001	1030	97.18

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	26	96.30
V2S	5	5	5	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.21	97.82	95.47	93.34	100.00	98.52	99.00	96.29

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:828) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 24 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 24 failures.

    • 1.lc_ctrl_stress_all_with_rand_reset.5303269928119548203706580971760714662072472295118545174067821919077555900860
      Line 10315, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/1.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 69624404492 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 69624404492 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 2.lc_ctrl_stress_all_with_rand_reset.85743159968188096845744544150280644848767528916589168478290137483804298504053
      Line 32866, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/2.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 23682485013 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 23682485013 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 22 more failures.

• UVM_ERROR (cip_base_vseq.sv:554) [lc_ctrl_common_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_state_error fired unexpectedly! has 2 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 2 failures.

    • 19.lc_ctrl_stress_all_with_rand_reset.1365222391607476275901930817656027131217783167689854820508441387001858021393
      Line 44916, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/19.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 220807969609 ps: (cip_base_vseq.sv:554) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
        UVM_INFO @ 220807969609 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 27.lc_ctrl_stress_all_with_rand_reset.78926726727973033401233279673728453170100192412055921364791806321525318657180
      Line 49777, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/27.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 124154673051 ps: (cip_base_vseq.sv:554) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
        UVM_INFO @ 124154673051 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_scoreboard.sv:301) scoreboard [scoreboard] alert fatal_prog_error did not trigger max_delay:* has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 23.lc_ctrl_stress_all_with_rand_reset.67029384424345951019071389426407740300836093009272859356278337746382673029944
      Line 20103, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/23.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 51960696048 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 51960696048 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (* [*] vs * [*]) has 1 failures:

  • Test lc_ctrl_errors has 1 failures.

    • 42.lc_ctrl_errors.46034320525071036968794092602154790522309719130350274846991141697122892026149
      Line 1691, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/42.lc_ctrl_errors/latest/run.log

        UVM_ERROR @  94646512 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
        UVM_INFO @  94646512 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Error-[CNST-STOF] Constraint solver timeout failure has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 47.lc_ctrl_stress_all_with_rand_reset.113049300394441103975184102960191091095409369771531165098259177456921045299346
      Line 33687, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/47.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        Error-[CNST-STOF] Constraint solver timeout failure
        ../src/lowrisc_dv_sec_cm_0/prim_sparse_fsm_flop_if.sv, 43
          Exceeded cpu time limit during solve.
          Please use the run-time switch +ntb_solver_cpu_limit to increase the cpu
          limit.  The default cpu limit is 1000 seconds per partition.
      

Past Results

• Latest
• 2024.06.10_06.39.02
• 2024.06.08_13.04.50
• 2024.06.07_04.48.20
• 2024.06.06_10.58.47
• 2024.06.05_03.50.58
• 2024.06.03_06.54.07
• 2024.05.31_04.46.01