LC_CTRL/VOLATILE_UNLOCK_DISABLED Simulation Results

Tuesday June 11 2024 19:02:38 UTC

GitHub Revision: dd5ad5fb77

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 66418170746903624595625818392428707033482455256751560525176982524210226376736

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	13.890s	949.568us	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.170s	53.751us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.130s	16.951us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	2.480s	220.784us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	1.980s	39.503us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	2.400s	34.519us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.130s	16.951us	20	20	100.00
		lc_ctrl_csr_aliasing	1.980s	39.503us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	11.720s	173.744us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	26.070s	380.323us	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	1.000s	13.715us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	4.860s	429.088us	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	38.160s	362.211us	50	50	100.00
V2	lc_errors	lc_ctrl_errors	26.380s	2.838ms	50	50	100.00
V2	security_escalation	lc_ctrl_state_failure	38.160s	362.211us	50	50	100.00
		lc_ctrl_prog_failure	4.860s	429.088us	50	50	100.00
		lc_ctrl_errors	26.380s	2.838ms	50	50	100.00
		lc_ctrl_security_escalation	15.110s	401.423us	50	50	100.00
		lc_ctrl_jtag_state_failure	1.472m	2.542ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	22.530s	821.141us	20	20	100.00
		lc_ctrl_jtag_errors	1.892m	4.239ms	20	20	100.00
V2	jtag_access	lc_ctrl_jtag_smoke	12.870s	2.130ms	20	20	100.00
		lc_ctrl_jtag_state_post_trans	33.360s	1.080ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	22.530s	821.141us	20	20	100.00
		lc_ctrl_jtag_errors	1.892m	4.239ms	20	20	100.00
		lc_ctrl_jtag_access	27.000s	5.676ms	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	36.830s	1.317ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	5.750s	240.800us	10	10	100.00
		lc_ctrl_jtag_csr_rw	4.390s	697.138us	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	25.120s	1.168ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	12.250s	1.012ms	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	1.890s	43.952us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	3.710s	505.817us	10	10	100.00
		lc_ctrl_jtag_alert_test	2.680s	171.319us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	19.130s	7.876ms	10	10	100.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.220s	31.889us	50	50	100.00
V2	stress_all	lc_ctrl_stress_all	11.868m	46.178ms	50	50	100.00
V2	alert_test	lc_ctrl_alert_test	1.280s	105.127us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	4.270s	190.867us	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	4.270s	190.867us	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.170s	53.751us	5	5	100.00
		lc_ctrl_csr_rw	1.130s	16.951us	20	20	100.00
		lc_ctrl_csr_aliasing	1.980s	39.503us	5	5	100.00
		lc_ctrl_same_csr_outstanding	2.030s	99.356us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.170s	53.751us	5	5	100.00
		lc_ctrl_csr_rw	1.130s	16.951us	20	20	100.00
		lc_ctrl_csr_aliasing	1.980s	39.503us	5	5	100.00
		lc_ctrl_same_csr_outstanding	2.030s	99.356us	20	20	100.00
V2		TOTAL			700	700	100.00
V2S	tl_intg_err	lc_ctrl_sec_cm	38.160s	2.860ms	5	5	100.00
		lc_ctrl_tl_intg_err	4.260s	116.175us	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	4.260s	116.175us	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	26.070s	380.323us	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	38.160s	362.211us	50	50	100.00
		lc_ctrl_sec_cm	38.160s	2.860ms	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	38.160s	362.211us	50	50	100.00
		lc_ctrl_sec_cm	38.160s	2.860ms	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	38.160s	362.211us	50	50	100.00
		lc_ctrl_sec_cm	38.160s	2.860ms	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	38.160s	362.211us	50	50	100.00
		lc_ctrl_sec_cm	38.160s	2.860ms	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	38.160s	362.211us	50	50	100.00
		lc_ctrl_sec_cm	38.160s	2.860ms	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	38.160s	362.211us	50	50	100.00
		lc_ctrl_sec_cm	38.160s	2.860ms	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	38.160s	362.211us	50	50	100.00
		lc_ctrl_sec_cm	38.160s	2.860ms	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	38.160s	362.211us	50	50	100.00
		lc_ctrl_sec_cm	38.160s	2.860ms	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	15.110s	401.423us	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	11.720s	173.744us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	33.360s	1.080ms	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	22.040s	937.155us	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	22.040s	937.155us	50	50	100.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	22.010s	615.125us	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	16.990s	2.137ms	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	16.990s	2.137ms	50	50	100.00
V2S		TOTAL			175	175	100.00
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	40.289m	45.571ms	22	50	44.00
V3		TOTAL			22	50	44.00
		TOTAL			1002	1030	97.28

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	27	100.00
V2S	5	5	5	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.24	97.92	95.75	93.38	100.00	98.52	99.00	96.11

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:828) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 23 failures:
  • Test lc_ctrl_stress_all_with_rand_reset has 23 failures.

    • 1.lc_ctrl_stress_all_with_rand_reset.15600559897964445604644600345918411208043359165346776332329730826886759892633
      Line 6876, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/1.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 7762328086 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 7762328086 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 3.lc_ctrl_stress_all_with_rand_reset.59775936561726636161020346366754236634281689649128205410780406113209382154674
      Line 3965, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/3.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 2898072460 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 2898072460 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 21 more failures.

• UVM_ERROR (cip_base_scoreboard.sv:301) scoreboard [scoreboard] alert fatal_prog_error did not trigger max_delay:* has 4 failures:
  • Test lc_ctrl_stress_all_with_rand_reset has 4 failures.

    • 11.lc_ctrl_stress_all_with_rand_reset.101381006381768285322066987916680185293617206097975517116713071006127268936570
      Line 19230, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/11.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 16617842153 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 16617842153 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 27.lc_ctrl_stress_all_with_rand_reset.67893466951444870486839895995346162692042720394147743256848536650430108064702
      Line 20358, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/27.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 62919942899 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 62919942899 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 2 more failures.

• UVM_ERROR (cip_base_vseq.sv:554) [lc_ctrl_common_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_state_error fired unexpectedly! has 1 failures:
  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 41.lc_ctrl_stress_all_with_rand_reset.8666867296026948805677996737867242569981244523219478903423502136839988136417
      Line 41429, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/41.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 56370657512 ps: (cip_base_vseq.sv:554) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
        UVM_INFO @ 56370657512 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

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