LC_CTRL/VOLATILE_UNLOCK_DISABLED Simulation Results

Thursday June 13 2024 19:02:12 UTC

GitHub Revision: 548a3880d8

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 95435389850697596633112362018639443702533575559488568730544091582583938649085

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	6.000s	188.159us	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.110s	19.699us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.160s	34.102us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	2.510s	155.527us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	1.730s	51.455us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	1.870s	102.108us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.160s	34.102us	20	20	100.00
		lc_ctrl_csr_aliasing	1.730s	51.455us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	11.720s	147.208us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	23.140s	398.169us	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	0.920s	10.914us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	5.930s	320.119us	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	39.650s	1.611ms	50	50	100.00
V2	lc_errors	lc_ctrl_errors	25.550s	2.667ms	50	50	100.00
V2	security_escalation	lc_ctrl_state_failure	39.650s	1.611ms	50	50	100.00
		lc_ctrl_prog_failure	5.930s	320.119us	50	50	100.00
		lc_ctrl_errors	25.550s	2.667ms	50	50	100.00
		lc_ctrl_security_escalation	16.050s	1.785ms	50	50	100.00
		lc_ctrl_jtag_state_failure	1.860m	13.134ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	13.980s	1.047ms	20	20	100.00
		lc_ctrl_jtag_errors	1.291m	2.802ms	20	20	100.00
V2	jtag_access	lc_ctrl_jtag_smoke	15.020s	5.854ms	20	20	100.00
		lc_ctrl_jtag_state_post_trans	22.390s	549.632us	20	20	100.00
		lc_ctrl_jtag_prog_failure	13.980s	1.047ms	20	20	100.00
		lc_ctrl_jtag_errors	1.291m	2.802ms	20	20	100.00
		lc_ctrl_jtag_access	22.700s	4.334ms	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	36.300s	5.143ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	3.020s	94.671us	10	10	100.00
		lc_ctrl_jtag_csr_rw	4.080s	155.776us	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	58.470s	5.330ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	18.660s	1.163ms	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	1.830s	191.466us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	4.100s	322.197us	10	10	100.00
		lc_ctrl_jtag_alert_test	2.870s	742.755us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	19.910s	9.975ms	10	10	100.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.090s	13.987us	50	50	100.00
V2	stress_all	lc_ctrl_stress_all	6.995m	12.559ms	50	50	100.00
V2	alert_test	lc_ctrl_alert_test	1.380s	33.116us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	6.110s	332.688us	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	6.110s	332.688us	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.110s	19.699us	5	5	100.00
		lc_ctrl_csr_rw	1.160s	34.102us	20	20	100.00
		lc_ctrl_csr_aliasing	1.730s	51.455us	5	5	100.00
		lc_ctrl_same_csr_outstanding	2.030s	98.649us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.110s	19.699us	5	5	100.00
		lc_ctrl_csr_rw	1.160s	34.102us	20	20	100.00
		lc_ctrl_csr_aliasing	1.730s	51.455us	5	5	100.00
		lc_ctrl_same_csr_outstanding	2.030s	98.649us	20	20	100.00
V2		TOTAL			700	700	100.00
V2S	tl_intg_err	lc_ctrl_sec_cm	38.700s	213.823us	5	5	100.00
		lc_ctrl_tl_intg_err	4.430s	111.940us	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	4.430s	111.940us	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	23.140s	398.169us	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	39.650s	1.611ms	50	50	100.00
		lc_ctrl_sec_cm	38.700s	213.823us	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	39.650s	1.611ms	50	50	100.00
		lc_ctrl_sec_cm	38.700s	213.823us	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	39.650s	1.611ms	50	50	100.00
		lc_ctrl_sec_cm	38.700s	213.823us	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	39.650s	1.611ms	50	50	100.00
		lc_ctrl_sec_cm	38.700s	213.823us	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	39.650s	1.611ms	50	50	100.00
		lc_ctrl_sec_cm	38.700s	213.823us	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	39.650s	1.611ms	50	50	100.00
		lc_ctrl_sec_cm	38.700s	213.823us	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	39.650s	1.611ms	50	50	100.00
		lc_ctrl_sec_cm	38.700s	213.823us	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	39.650s	1.611ms	50	50	100.00
		lc_ctrl_sec_cm	38.700s	213.823us	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	16.050s	1.785ms	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	11.720s	147.208us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	22.390s	549.632us	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	23.230s	803.955us	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	23.230s	803.955us	50	50	100.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	27.310s	8.393ms	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	14.650s	2.540ms	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	14.650s	2.540ms	50	50	100.00
V2S		TOTAL			175	175	100.00
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	53.967m	142.543ms	21	50	42.00
V3		TOTAL			21	50	42.00
		TOTAL			1001	1030	97.18

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	27	100.00
V2S	5	5	5	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.24	97.92	95.66	93.38	100.00	98.52	98.76	96.47

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:828) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 28 failures:
  • Test lc_ctrl_stress_all_with_rand_reset has 28 failures.

    • 0.lc_ctrl_stress_all_with_rand_reset.80364942514958902215677620491648345697126182514158615174858322475944199923023
      Line 40950, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/0.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 79497516845 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 79497516845 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 1.lc_ctrl_stress_all_with_rand_reset.33665043301373001585491441037539578686057323386295210464756374546653591743671
      Line 47097, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/1.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 125890030150 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 125890030150 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 26 more failures.

• UVM_ERROR (cip_base_vseq.sv:554) [lc_ctrl_common_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_state_error fired unexpectedly! has 1 failures:
  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 7.lc_ctrl_stress_all_with_rand_reset.15578918465264579284360843411853273190658809917741875499077750447007143576070
      Line 5443, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/7.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 27092112702 ps: (cip_base_vseq.sv:554) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
        UVM_INFO @ 27092112702 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

• Latest
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