LC_CTRL/VOLATILE_UNLOCK_DISABLED Simulation Results

Friday June 21 2024 23:02:45 UTC

GitHub Revision: de38ce313c

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 40294666978553523170681160506532247841705182588034413483474981853853670477454

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	14.280s	267.792us	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.150s	230.155us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.140s	17.885us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	2.690s	256.825us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	1.350s	345.404us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	1.910s	89.151us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.140s	17.885us	20	20	100.00
		lc_ctrl_csr_aliasing	1.350s	345.404us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	9.950s	477.168us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	19.440s	363.357us	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	1.000s	13.815us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	5.570s	569.600us	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	36.130s	817.031us	50	50	100.00
V2	lc_errors	lc_ctrl_errors	25.870s	745.539us	50	50	100.00
V2	security_escalation	lc_ctrl_state_failure	36.130s	817.031us	50	50	100.00
		lc_ctrl_prog_failure	5.570s	569.600us	50	50	100.00
		lc_ctrl_errors	25.870s	745.539us	50	50	100.00
		lc_ctrl_security_escalation	14.440s	373.533us	50	50	100.00
		lc_ctrl_jtag_state_failure	1.629m	5.944ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	23.040s	804.672us	20	20	100.00
		lc_ctrl_jtag_errors	1.131m	5.272ms	20	20	100.00
V2	jtag_access	lc_ctrl_jtag_smoke	10.590s	657.234us	20	20	100.00
		lc_ctrl_jtag_state_post_trans	36.950s	1.244ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	23.040s	804.672us	20	20	100.00
		lc_ctrl_jtag_errors	1.131m	5.272ms	20	20	100.00
		lc_ctrl_jtag_access	23.620s	12.626ms	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	30.990s	4.250ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	4.440s	315.265us	10	10	100.00
		lc_ctrl_jtag_csr_rw	4.320s	702.128us	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	29.720s	8.215ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	14.920s	4.775ms	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	1.850s	77.693us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	2.740s	165.866us	10	10	100.00
		lc_ctrl_jtag_alert_test	1.950s	58.156us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	15.290s	1.388ms	10	10	100.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.230s	14.721us	50	50	100.00
V2	stress_all	lc_ctrl_stress_all	7.287m	52.407ms	49	50	98.00
V2	alert_test	lc_ctrl_alert_test	1.320s	85.908us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	5.060s	268.671us	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	5.060s	268.671us	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.150s	230.155us	5	5	100.00
		lc_ctrl_csr_rw	1.140s	17.885us	20	20	100.00
		lc_ctrl_csr_aliasing	1.350s	345.404us	5	5	100.00
		lc_ctrl_same_csr_outstanding	2.080s	51.010us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.150s	230.155us	5	5	100.00
		lc_ctrl_csr_rw	1.140s	17.885us	20	20	100.00
		lc_ctrl_csr_aliasing	1.350s	345.404us	5	5	100.00
		lc_ctrl_same_csr_outstanding	2.080s	51.010us	20	20	100.00
V2		TOTAL			699	700	99.86
V2S	tl_intg_err	lc_ctrl_sec_cm	35.200s	873.013us	5	5	100.00
		lc_ctrl_tl_intg_err	4.420s	835.309us	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	4.420s	835.309us	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	19.440s	363.357us	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	36.130s	817.031us	50	50	100.00
		lc_ctrl_sec_cm	35.200s	873.013us	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	36.130s	817.031us	50	50	100.00
		lc_ctrl_sec_cm	35.200s	873.013us	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	36.130s	817.031us	50	50	100.00
		lc_ctrl_sec_cm	35.200s	873.013us	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	36.130s	817.031us	50	50	100.00
		lc_ctrl_sec_cm	35.200s	873.013us	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	36.130s	817.031us	50	50	100.00
		lc_ctrl_sec_cm	35.200s	873.013us	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	36.130s	817.031us	50	50	100.00
		lc_ctrl_sec_cm	35.200s	873.013us	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	36.130s	817.031us	50	50	100.00
		lc_ctrl_sec_cm	35.200s	873.013us	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	36.130s	817.031us	50	50	100.00
		lc_ctrl_sec_cm	35.200s	873.013us	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	14.440s	373.533us	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	9.950s	477.168us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	36.950s	1.244ms	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	27.270s	2.571ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	27.270s	2.571ms	50	50	100.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	22.300s	3.975ms	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	21.880s	1.613ms	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	21.880s	1.613ms	50	50	100.00
V2S		TOTAL			175	175	100.00
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	45.482m	102.439ms	20	50	40.00
V3		TOTAL			20	50	40.00
		TOTAL			999	1030	96.99

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	26	96.30
V2S	5	5	5	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.22	97.92	95.66	93.38	100.00	98.52	98.76	96.29

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:828) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 27 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 27 failures.

    • 0.lc_ctrl_stress_all_with_rand_reset.76612771287565465388479778426900640877502506071058173868965896594079578146743
      Line 19963, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/0.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 67940593329 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 67940593329 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 1.lc_ctrl_stress_all_with_rand_reset.22634529154957840998850843667509595726599222256177148223105319436872280798278
      Line 18157, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/1.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 28797085963 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 28797085963 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 25 more failures.

• UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (* [*] vs * [*]) has 2 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 30.lc_ctrl_stress_all_with_rand_reset.91743226498671649882563541547712511499508878287962363198022308230708932331143
      Line 9828, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/30.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 24153849230 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 24153849230 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test lc_ctrl_stress_all has 1 failures.

    • 45.lc_ctrl_stress_all.73266515434505899663085627623137396826752137582905657981341568740278835504336
      Line 4250, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/45.lc_ctrl_stress_all/latest/run.log

        UVM_ERROR @ 2761727340 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 2761727340 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Job lc_ctrl_volatile_unlock_disabled-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 26.lc_ctrl_stress_all_with_rand_reset.62928042414116775723714394563756788753068382020993169082386840143442715824503
      Log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/26.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        Job ID: smart:1843fa84-c028-414e-9801-a2af9531c4bb
      

• UVM_ERROR (cip_base_vseq.sv:554) [lc_ctrl_common_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_state_error fired unexpectedly! has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 49.lc_ctrl_stress_all_with_rand_reset.99585050027688455966910724898379878096281483706314431268923076781695183550943
      Line 16446, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/49.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 49239134412 ps: (cip_base_vseq.sv:554) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
        UVM_INFO @ 49239134412 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

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