LC_CTRL/VOLATILE_UNLOCK_DISABLED Simulation Results

Saturday June 22 2024 23:02:20 UTC

GitHub Revision: 8fdb25c8d9

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 116774179587740886356693500529232784059703555433764635649168222249757162669

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	8.620s	242.434us	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.120s	24.377us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.200s	18.478us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	1.860s	47.519us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	1.800s	39.363us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	2.440s	33.401us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.200s	18.478us	20	20	100.00
		lc_ctrl_csr_aliasing	1.800s	39.363us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	10.400s	74.198us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	25.530s	2.143ms	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	0.970s	10.897us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	5.260s	506.179us	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	37.600s	364.463us	50	50	100.00
V2	lc_errors	lc_ctrl_errors	23.900s	2.519ms	50	50	100.00
V2	security_escalation	lc_ctrl_state_failure	37.600s	364.463us	50	50	100.00
		lc_ctrl_prog_failure	5.260s	506.179us	50	50	100.00
		lc_ctrl_errors	23.900s	2.519ms	50	50	100.00
		lc_ctrl_security_escalation	14.430s	3.015ms	50	50	100.00
		lc_ctrl_jtag_state_failure	1.524m	21.467ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	18.660s	718.374us	20	20	100.00
		lc_ctrl_jtag_errors	1.096m	9.545ms	20	20	100.00
V2	jtag_access	lc_ctrl_jtag_smoke	18.780s	746.108us	20	20	100.00
		lc_ctrl_jtag_state_post_trans	31.710s	1.830ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	18.660s	718.374us	20	20	100.00
		lc_ctrl_jtag_errors	1.096m	9.545ms	20	20	100.00
		lc_ctrl_jtag_access	34.210s	16.745ms	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	36.140s	1.375ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	3.500s	111.458us	10	10	100.00
		lc_ctrl_jtag_csr_rw	2.130s	176.635us	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	43.040s	2.068ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	25.620s	4.273ms	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	1.490s	86.229us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	3.820s	296.274us	10	10	100.00
		lc_ctrl_jtag_alert_test	1.670s	358.201us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	18.120s	3.097ms	10	10	100.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.210s	17.800us	50	50	100.00
V2	stress_all	lc_ctrl_stress_all	7.268m	11.648ms	50	50	100.00
V2	alert_test	lc_ctrl_alert_test	1.320s	24.704us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	5.840s	710.404us	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	5.840s	710.404us	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.120s	24.377us	5	5	100.00
		lc_ctrl_csr_rw	1.200s	18.478us	20	20	100.00
		lc_ctrl_csr_aliasing	1.800s	39.363us	5	5	100.00
		lc_ctrl_same_csr_outstanding	2.110s	47.150us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.120s	24.377us	5	5	100.00
		lc_ctrl_csr_rw	1.200s	18.478us	20	20	100.00
		lc_ctrl_csr_aliasing	1.800s	39.363us	5	5	100.00
		lc_ctrl_same_csr_outstanding	2.110s	47.150us	20	20	100.00
V2		TOTAL			700	700	100.00
V2S	tl_intg_err	lc_ctrl_sec_cm	40.950s	908.645us	5	5	100.00
		lc_ctrl_tl_intg_err	4.250s	125.926us	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	4.250s	125.926us	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	25.530s	2.143ms	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	37.600s	364.463us	50	50	100.00
		lc_ctrl_sec_cm	40.950s	908.645us	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	37.600s	364.463us	50	50	100.00
		lc_ctrl_sec_cm	40.950s	908.645us	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	37.600s	364.463us	50	50	100.00
		lc_ctrl_sec_cm	40.950s	908.645us	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	37.600s	364.463us	50	50	100.00
		lc_ctrl_sec_cm	40.950s	908.645us	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	37.600s	364.463us	50	50	100.00
		lc_ctrl_sec_cm	40.950s	908.645us	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	37.600s	364.463us	50	50	100.00
		lc_ctrl_sec_cm	40.950s	908.645us	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	37.600s	364.463us	50	50	100.00
		lc_ctrl_sec_cm	40.950s	908.645us	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	37.600s	364.463us	50	50	100.00
		lc_ctrl_sec_cm	40.950s	908.645us	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	14.430s	3.015ms	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	10.400s	74.198us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	31.710s	1.830ms	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	25.580s	1.761ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	25.580s	1.761ms	50	50	100.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	24.810s	2.444ms	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	20.450s	1.392ms	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	20.450s	1.392ms	50	50	100.00
V2S		TOTAL			175	175	100.00
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	34.813m	291.870ms	25	50	50.00
V3		TOTAL			25	50	50.00
		TOTAL			1005	1030	97.57

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	27	100.00
V2S	5	5	5	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.27	97.92	96.03	93.38	100.00	98.52	98.76	96.29

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:828) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 20 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 20 failures.

    • 0.lc_ctrl_stress_all_with_rand_reset.101033150512979812339905477966767239969071917859378337620742223131400832755951
      Line 38599, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/0.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 30315894502 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 30315894502 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 5.lc_ctrl_stress_all_with_rand_reset.82340736116249767699628262988788337907747030257463955270919829925434112023594
      Line 10017, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/5.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 22846264336 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 22846264336 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 18 more failures.

• UVM_ERROR (cip_base_vseq.sv:554) [lc_ctrl_common_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_state_error fired unexpectedly! has 2 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 2 failures.

    • 6.lc_ctrl_stress_all_with_rand_reset.107451765068027244270253256211632299843086711731059528432760648631566479128129
      Line 34858, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/6.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 24959035875 ps: (cip_base_vseq.sv:554) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
        UVM_INFO @ 24959035875 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 25.lc_ctrl_stress_all_with_rand_reset.69743880006299405348686631678898484408292146027903006310468945847061202545504
      Line 21619, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/25.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 288667416343 ps: (cip_base_vseq.sv:554) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
        UVM_INFO @ 288667416343 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_scoreboard.sv:301) scoreboard [scoreboard] alert fatal_prog_error did not trigger max_delay:* has 2 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 2 failures.

    • 7.lc_ctrl_stress_all_with_rand_reset.55947863399286580863171324192272049620686759838905524475331556897986809761705
      Line 10051, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/7.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 11301396463 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 11301396463 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 27.lc_ctrl_stress_all_with_rand_reset.63175643234717378332636403144286710734937582056716596191524113068802912564040
      Line 26323, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/27.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 14007743722 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 14007743722 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:752) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 20.lc_ctrl_stress_all_with_rand_reset.16703480750542257821761484353816387713799341123900440967474212151576002659381
      Line 34462, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/20.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 22862519513 ps: (cip_base_vseq.sv:752) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
        UVM_INFO @ 22862519513 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

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