LC_CTRL/VOLATILE_UNLOCK_DISABLED Simulation Results

Sunday June 23 2024 23:02:35 UTC

GitHub Revision: 25e609d6bb

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 43520053114197278442322840927374150239284669988213580416404649115121474470865

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	9.680s	140.381us	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.080s	38.665us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.090s	14.983us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	1.840s	368.197us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	1.760s	34.379us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	2.010s	32.272us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.090s	14.983us	20	20	100.00
		lc_ctrl_csr_aliasing	1.760s	34.379us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	11.220s	132.359us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	19.120s	3.840ms	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	1.020s	13.808us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	8.150s	973.528us	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	36.650s	339.017us	50	50	100.00
V2	lc_errors	lc_ctrl_errors	26.280s	4.396ms	50	50	100.00
V2	security_escalation	lc_ctrl_state_failure	36.650s	339.017us	50	50	100.00
		lc_ctrl_prog_failure	8.150s	973.528us	50	50	100.00
		lc_ctrl_errors	26.280s	4.396ms	50	50	100.00
		lc_ctrl_security_escalation	18.660s	2.229ms	50	50	100.00
		lc_ctrl_jtag_state_failure	1.624m	5.465ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	21.730s	826.249us	20	20	100.00
		lc_ctrl_jtag_errors	1.112m	2.363ms	20	20	100.00
V2	jtag_access	lc_ctrl_jtag_smoke	13.200s	922.548us	20	20	100.00
		lc_ctrl_jtag_state_post_trans	23.950s	5.383ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	21.730s	826.249us	20	20	100.00
		lc_ctrl_jtag_errors	1.112m	2.363ms	20	20	100.00
		lc_ctrl_jtag_access	17.950s	738.196us	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	36.170s	8.513ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	4.380s	634.237us	10	10	100.00
		lc_ctrl_jtag_csr_rw	3.990s	287.067us	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	35.950s	4.105ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	12.970s	4.162ms	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	1.760s	356.579us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	3.390s	358.932us	10	10	100.00
		lc_ctrl_jtag_alert_test	2.030s	63.694us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	20.610s	4.629ms	10	10	100.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.230s	34.129us	50	50	100.00
V2	stress_all	lc_ctrl_stress_all	9.780m	25.459ms	50	50	100.00
V2	alert_test	lc_ctrl_alert_test	1.490s	30.460us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	4.920s	352.264us	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	4.920s	352.264us	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.080s	38.665us	5	5	100.00
		lc_ctrl_csr_rw	1.090s	14.983us	20	20	100.00
		lc_ctrl_csr_aliasing	1.760s	34.379us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.950s	40.550us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.080s	38.665us	5	5	100.00
		lc_ctrl_csr_rw	1.090s	14.983us	20	20	100.00
		lc_ctrl_csr_aliasing	1.760s	34.379us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.950s	40.550us	20	20	100.00
V2		TOTAL			700	700	100.00
V2S	tl_intg_err	lc_ctrl_sec_cm	37.560s	1.564ms	5	5	100.00
		lc_ctrl_tl_intg_err	6.250s	930.001us	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	6.250s	930.001us	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	19.120s	3.840ms	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	36.650s	339.017us	50	50	100.00
		lc_ctrl_sec_cm	37.560s	1.564ms	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	36.650s	339.017us	50	50	100.00
		lc_ctrl_sec_cm	37.560s	1.564ms	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	36.650s	339.017us	50	50	100.00
		lc_ctrl_sec_cm	37.560s	1.564ms	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	36.650s	339.017us	50	50	100.00
		lc_ctrl_sec_cm	37.560s	1.564ms	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	36.650s	339.017us	50	50	100.00
		lc_ctrl_sec_cm	37.560s	1.564ms	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	36.650s	339.017us	50	50	100.00
		lc_ctrl_sec_cm	37.560s	1.564ms	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	36.650s	339.017us	50	50	100.00
		lc_ctrl_sec_cm	37.560s	1.564ms	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	36.650s	339.017us	50	50	100.00
		lc_ctrl_sec_cm	37.560s	1.564ms	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	18.660s	2.229ms	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	11.220s	132.359us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	23.950s	5.383ms	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	24.790s	2.446ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	24.790s	2.446ms	50	50	100.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	25.390s	1.148ms	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	20.340s	757.241us	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	20.340s	757.241us	50	50	100.00
V2S		TOTAL			175	175	100.00
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	1.739h	81.260ms	25	50	50.00
V3		TOTAL			25	50	50.00
		TOTAL			1005	1030	97.57

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	27	100.00
V2S	5	5	5	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.89	97.92	95.93	93.38	97.62	98.52	98.76	96.11

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:828) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 21 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 21 failures.

    • 2.lc_ctrl_stress_all_with_rand_reset.71715164708733801332849192870086272082148315915952627707208654504240790962053
      Line 2217, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/2.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 2877679082 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 2877679082 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 3.lc_ctrl_stress_all_with_rand_reset.39558658714480839513716088959022085780299209475330511715143719746510975777736
      Line 21282, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/3.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 67528177232 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 67528177232 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 19 more failures.

• Error-[CNST-STOF] Constraint solver timeout failure has 2 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 2 failures.

    • 7.lc_ctrl_stress_all_with_rand_reset.103715781868139876232406596251027532123761446753534243211912514647620911955657
      Line 37434, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/7.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        Error-[CNST-STOF] Constraint solver timeout failure
        ../src/lowrisc_dv_sec_cm_0/prim_sparse_fsm_flop_if.sv, 43
          Exceeded cpu time limit during solve.
          Please use the run-time switch +ntb_solver_cpu_limit to increase the cpu
          limit.  The default cpu limit is 1000 seconds per partition.
      

    • 36.lc_ctrl_stress_all_with_rand_reset.18039995247360665045437202105184163521410882197045626431297143655863981722797
      Line 37520, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/36.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        Error-[CNST-STOF] Constraint solver timeout failure
        ../src/lowrisc_dv_sec_cm_0/prim_sparse_fsm_flop_if.sv, 43
          Exceeded cpu time limit during solve.
          Please use the run-time switch +ntb_solver_cpu_limit to increase the cpu
          limit.  The default cpu limit is 1000 seconds per partition.
      

• UVM_ERROR (cip_base_vseq.sv:554) [lc_ctrl_common_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_state_error fired unexpectedly! has 2 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 2 failures.

    • 9.lc_ctrl_stress_all_with_rand_reset.69261674796295710083442852460284340253397412109134019417088714541548111377227
      Line 38297, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/9.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 53224886758 ps: (cip_base_vseq.sv:554) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
        UVM_INFO @ 53224886758 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 19.lc_ctrl_stress_all_with_rand_reset.8523129934929259873297990468483262321013830822164973870614555906677839726284
      Line 29686, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/19.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 41093727099 ps: (cip_base_vseq.sv:554) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
        UVM_INFO @ 41093727099 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

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