LC_CTRL/VOLATILE_UNLOCK_DISABLED Simulation Results

Monday June 24 2024 23:02:35 UTC

GitHub Revision: 6e698b4dfe

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 102849012855470111388983783327793201144267754054590670930996118558901483180117

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke lc_ctrl_smoke 6.370s 112.452us 50 50 100.00
V1 csr_hw_reset lc_ctrl_csr_hw_reset 1.210s 65.076us 5 5 100.00
V1 csr_rw lc_ctrl_csr_rw 1.200s 20.092us 20 20 100.00
V1 csr_bit_bash lc_ctrl_csr_bit_bash 3.210s 182.066us 5 5 100.00
V1 csr_aliasing lc_ctrl_csr_aliasing 1.810s 160.133us 5 5 100.00
V1 csr_mem_rw_with_rand_reset lc_ctrl_csr_mem_rw_with_rand_reset 1.900s 98.774us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr lc_ctrl_csr_rw 1.200s 20.092us 20 20 100.00
lc_ctrl_csr_aliasing 1.810s 160.133us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 state_post_trans lc_ctrl_state_post_trans 10.950s 156.334us 50 50 100.00
V2 regwen_during_op lc_ctrl_regwen_during_op 18.100s 305.976us 10 10 100.00
V2 rand_wr_claim_transition_if lc_ctrl_claim_transition_if 0.970s 12.808us 10 10 100.00
V2 lc_prog_failure lc_ctrl_prog_failure 4.320s 98.424us 50 50 100.00
V2 lc_state_failure lc_ctrl_state_failure 42.160s 377.184us 50 50 100.00
V2 lc_errors lc_ctrl_errors 28.500s 2.649ms 50 50 100.00
V2 security_escalation lc_ctrl_state_failure 42.160s 377.184us 50 50 100.00
lc_ctrl_prog_failure 4.320s 98.424us 50 50 100.00
lc_ctrl_errors 28.500s 2.649ms 50 50 100.00
lc_ctrl_security_escalation 13.440s 1.047ms 50 50 100.00
lc_ctrl_jtag_state_failure 1.775m 11.805ms 20 20 100.00
lc_ctrl_jtag_prog_failure 32.070s 4.724ms 20 20 100.00
lc_ctrl_jtag_errors 1.539m 13.424ms 20 20 100.00
V2 jtag_access lc_ctrl_jtag_smoke 12.390s 1.786ms 20 20 100.00
lc_ctrl_jtag_state_post_trans 29.700s 5.759ms 20 20 100.00
lc_ctrl_jtag_prog_failure 32.070s 4.724ms 20 20 100.00
lc_ctrl_jtag_errors 1.539m 13.424ms 20 20 100.00
lc_ctrl_jtag_access 34.800s 1.496ms 50 50 100.00
lc_ctrl_jtag_regwen_during_op 37.960s 2.772ms 10 10 100.00
lc_ctrl_jtag_csr_hw_reset 4.220s 278.256us 10 10 100.00
lc_ctrl_jtag_csr_rw 3.690s 129.766us 10 10 100.00
lc_ctrl_jtag_csr_bit_bash 46.900s 8.512ms 10 10 100.00
lc_ctrl_jtag_csr_aliasing 20.320s 3.863ms 10 10 100.00
lc_ctrl_jtag_same_csr_outstanding 1.840s 149.718us 10 10 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 7.220s 308.583us 10 10 100.00
lc_ctrl_jtag_alert_test 2.280s 196.596us 10 10 100.00
V2 jtag_priority lc_ctrl_jtag_priority 24.550s 2.206ms 10 10 100.00
V2 lc_ctrl_volatile_unlock lc_ctrl_volatile_unlock_smoke 1.410s 24.758us 50 50 100.00
V2 stress_all lc_ctrl_stress_all 10.528m 105.840ms 48 50 96.00
V2 alert_test lc_ctrl_alert_test 1.320s 24.042us 50 50 100.00
V2 tl_d_oob_addr_access lc_ctrl_tl_errors 5.310s 546.751us 20 20 100.00
V2 tl_d_illegal_access lc_ctrl_tl_errors 5.310s 546.751us 20 20 100.00
V2 tl_d_outstanding_access lc_ctrl_csr_hw_reset 1.210s 65.076us 5 5 100.00
lc_ctrl_csr_rw 1.200s 20.092us 20 20 100.00
lc_ctrl_csr_aliasing 1.810s 160.133us 5 5 100.00
lc_ctrl_same_csr_outstanding 2.020s 169.011us 20 20 100.00
V2 tl_d_partial_access lc_ctrl_csr_hw_reset 1.210s 65.076us 5 5 100.00
lc_ctrl_csr_rw 1.200s 20.092us 20 20 100.00
lc_ctrl_csr_aliasing 1.810s 160.133us 5 5 100.00
lc_ctrl_same_csr_outstanding 2.020s 169.011us 20 20 100.00
V2 TOTAL 698 700 99.71
V2S tl_intg_err lc_ctrl_sec_cm 36.220s 231.823us 5 5 100.00
lc_ctrl_tl_intg_err 3.530s 298.901us 20 20 100.00
V2S sec_cm_bus_integrity lc_ctrl_tl_intg_err 3.530s 298.901us 20 20 100.00
V2S sec_cm_transition_config_regwen lc_ctrl_regwen_during_op 18.100s 305.976us 10 10 100.00
V2S sec_cm_manuf_state_sparse lc_ctrl_state_failure 42.160s 377.184us 50 50 100.00
lc_ctrl_sec_cm 36.220s 231.823us 5 5 100.00
V2S sec_cm_transition_ctr_sparse lc_ctrl_state_failure 42.160s 377.184us 50 50 100.00
lc_ctrl_sec_cm 36.220s 231.823us 5 5 100.00
V2S sec_cm_manuf_state_bkgn_chk lc_ctrl_state_failure 42.160s 377.184us 50 50 100.00
lc_ctrl_sec_cm 36.220s 231.823us 5 5 100.00
V2S sec_cm_transition_ctr_bkgn_chk lc_ctrl_state_failure 42.160s 377.184us 50 50 100.00
lc_ctrl_sec_cm 36.220s 231.823us 5 5 100.00
V2S sec_cm_state_config_sparse lc_ctrl_state_failure 42.160s 377.184us 50 50 100.00
lc_ctrl_sec_cm 36.220s 231.823us 5 5 100.00
V2S sec_cm_main_fsm_sparse lc_ctrl_state_failure 42.160s 377.184us 50 50 100.00
lc_ctrl_sec_cm 36.220s 231.823us 5 5 100.00
V2S sec_cm_kmac_fsm_sparse lc_ctrl_state_failure 42.160s 377.184us 50 50 100.00
lc_ctrl_sec_cm 36.220s 231.823us 5 5 100.00
V2S sec_cm_main_fsm_local_esc lc_ctrl_state_failure 42.160s 377.184us 50 50 100.00
lc_ctrl_sec_cm 36.220s 231.823us 5 5 100.00
V2S sec_cm_main_fsm_global_esc lc_ctrl_security_escalation 13.440s 1.047ms 50 50 100.00
V2S sec_cm_main_ctrl_flow_consistency lc_ctrl_state_post_trans 10.950s 156.334us 50 50 100.00
lc_ctrl_jtag_state_post_trans 29.700s 5.759ms 20 20 100.00
V2S sec_cm_intersig_mubi lc_ctrl_sec_mubi 22.080s 2.190ms 50 50 100.00
V2S sec_cm_token_valid_ctrl_mubi lc_ctrl_sec_mubi 22.080s 2.190ms 50 50 100.00
V2S sec_cm_token_digest lc_ctrl_sec_token_digest 28.650s 1.168ms 50 50 100.00
V2S sec_cm_token_mux_ctrl_redun lc_ctrl_sec_token_mux 20.660s 670.285us 50 50 100.00
V2S sec_cm_token_valid_mux_redun lc_ctrl_sec_token_mux 20.660s 670.285us 50 50 100.00
V2S TOTAL 175 175 100.00
V3 stress_all_with_rand_reset lc_ctrl_stress_all_with_rand_reset 40.956m 33.579ms 27 50 54.00
V3 TOTAL 27 50 54.00
TOTAL 1005 1030 97.57

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 27 27 26 96.30
V2S 5 5 5 100.00
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
97.17 97.92 95.56 93.38 100.00 98.52 98.51 96.29

Failure Buckets

Past Results