6e698b4dfe
Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
---|---|---|---|---|---|---|---|
V1 | smoke | lc_ctrl_smoke | 6.370s | 112.452us | 50 | 50 | 100.00 |
V1 | csr_hw_reset | lc_ctrl_csr_hw_reset | 1.210s | 65.076us | 5 | 5 | 100.00 |
V1 | csr_rw | lc_ctrl_csr_rw | 1.200s | 20.092us | 20 | 20 | 100.00 |
V1 | csr_bit_bash | lc_ctrl_csr_bit_bash | 3.210s | 182.066us | 5 | 5 | 100.00 |
V1 | csr_aliasing | lc_ctrl_csr_aliasing | 1.810s | 160.133us | 5 | 5 | 100.00 |
V1 | csr_mem_rw_with_rand_reset | lc_ctrl_csr_mem_rw_with_rand_reset | 1.900s | 98.774us | 20 | 20 | 100.00 |
V1 | regwen_csr_and_corresponding_lockable_csr | lc_ctrl_csr_rw | 1.200s | 20.092us | 20 | 20 | 100.00 |
lc_ctrl_csr_aliasing | 1.810s | 160.133us | 5 | 5 | 100.00 | ||
V1 | TOTAL | 105 | 105 | 100.00 | |||
V2 | state_post_trans | lc_ctrl_state_post_trans | 10.950s | 156.334us | 50 | 50 | 100.00 |
V2 | regwen_during_op | lc_ctrl_regwen_during_op | 18.100s | 305.976us | 10 | 10 | 100.00 |
V2 | rand_wr_claim_transition_if | lc_ctrl_claim_transition_if | 0.970s | 12.808us | 10 | 10 | 100.00 |
V2 | lc_prog_failure | lc_ctrl_prog_failure | 4.320s | 98.424us | 50 | 50 | 100.00 |
V2 | lc_state_failure | lc_ctrl_state_failure | 42.160s | 377.184us | 50 | 50 | 100.00 |
V2 | lc_errors | lc_ctrl_errors | 28.500s | 2.649ms | 50 | 50 | 100.00 |
V2 | security_escalation | lc_ctrl_state_failure | 42.160s | 377.184us | 50 | 50 | 100.00 |
lc_ctrl_prog_failure | 4.320s | 98.424us | 50 | 50 | 100.00 | ||
lc_ctrl_errors | 28.500s | 2.649ms | 50 | 50 | 100.00 | ||
lc_ctrl_security_escalation | 13.440s | 1.047ms | 50 | 50 | 100.00 | ||
lc_ctrl_jtag_state_failure | 1.775m | 11.805ms | 20 | 20 | 100.00 | ||
lc_ctrl_jtag_prog_failure | 32.070s | 4.724ms | 20 | 20 | 100.00 | ||
lc_ctrl_jtag_errors | 1.539m | 13.424ms | 20 | 20 | 100.00 | ||
V2 | jtag_access | lc_ctrl_jtag_smoke | 12.390s | 1.786ms | 20 | 20 | 100.00 |
lc_ctrl_jtag_state_post_trans | 29.700s | 5.759ms | 20 | 20 | 100.00 | ||
lc_ctrl_jtag_prog_failure | 32.070s | 4.724ms | 20 | 20 | 100.00 | ||
lc_ctrl_jtag_errors | 1.539m | 13.424ms | 20 | 20 | 100.00 | ||
lc_ctrl_jtag_access | 34.800s | 1.496ms | 50 | 50 | 100.00 | ||
lc_ctrl_jtag_regwen_during_op | 37.960s | 2.772ms | 10 | 10 | 100.00 | ||
lc_ctrl_jtag_csr_hw_reset | 4.220s | 278.256us | 10 | 10 | 100.00 | ||
lc_ctrl_jtag_csr_rw | 3.690s | 129.766us | 10 | 10 | 100.00 | ||
lc_ctrl_jtag_csr_bit_bash | 46.900s | 8.512ms | 10 | 10 | 100.00 | ||
lc_ctrl_jtag_csr_aliasing | 20.320s | 3.863ms | 10 | 10 | 100.00 | ||
lc_ctrl_jtag_same_csr_outstanding | 1.840s | 149.718us | 10 | 10 | 100.00 | ||
lc_ctrl_jtag_csr_mem_rw_with_rand_reset | 7.220s | 308.583us | 10 | 10 | 100.00 | ||
lc_ctrl_jtag_alert_test | 2.280s | 196.596us | 10 | 10 | 100.00 | ||
V2 | jtag_priority | lc_ctrl_jtag_priority | 24.550s | 2.206ms | 10 | 10 | 100.00 |
V2 | lc_ctrl_volatile_unlock | lc_ctrl_volatile_unlock_smoke | 1.410s | 24.758us | 50 | 50 | 100.00 |
V2 | stress_all | lc_ctrl_stress_all | 10.528m | 105.840ms | 48 | 50 | 96.00 |
V2 | alert_test | lc_ctrl_alert_test | 1.320s | 24.042us | 50 | 50 | 100.00 |
V2 | tl_d_oob_addr_access | lc_ctrl_tl_errors | 5.310s | 546.751us | 20 | 20 | 100.00 |
V2 | tl_d_illegal_access | lc_ctrl_tl_errors | 5.310s | 546.751us | 20 | 20 | 100.00 |
V2 | tl_d_outstanding_access | lc_ctrl_csr_hw_reset | 1.210s | 65.076us | 5 | 5 | 100.00 |
lc_ctrl_csr_rw | 1.200s | 20.092us | 20 | 20 | 100.00 | ||
lc_ctrl_csr_aliasing | 1.810s | 160.133us | 5 | 5 | 100.00 | ||
lc_ctrl_same_csr_outstanding | 2.020s | 169.011us | 20 | 20 | 100.00 | ||
V2 | tl_d_partial_access | lc_ctrl_csr_hw_reset | 1.210s | 65.076us | 5 | 5 | 100.00 |
lc_ctrl_csr_rw | 1.200s | 20.092us | 20 | 20 | 100.00 | ||
lc_ctrl_csr_aliasing | 1.810s | 160.133us | 5 | 5 | 100.00 | ||
lc_ctrl_same_csr_outstanding | 2.020s | 169.011us | 20 | 20 | 100.00 | ||
V2 | TOTAL | 698 | 700 | 99.71 | |||
V2S | tl_intg_err | lc_ctrl_sec_cm | 36.220s | 231.823us | 5 | 5 | 100.00 |
lc_ctrl_tl_intg_err | 3.530s | 298.901us | 20 | 20 | 100.00 | ||
V2S | sec_cm_bus_integrity | lc_ctrl_tl_intg_err | 3.530s | 298.901us | 20 | 20 | 100.00 |
V2S | sec_cm_transition_config_regwen | lc_ctrl_regwen_during_op | 18.100s | 305.976us | 10 | 10 | 100.00 |
V2S | sec_cm_manuf_state_sparse | lc_ctrl_state_failure | 42.160s | 377.184us | 50 | 50 | 100.00 |
lc_ctrl_sec_cm | 36.220s | 231.823us | 5 | 5 | 100.00 | ||
V2S | sec_cm_transition_ctr_sparse | lc_ctrl_state_failure | 42.160s | 377.184us | 50 | 50 | 100.00 |
lc_ctrl_sec_cm | 36.220s | 231.823us | 5 | 5 | 100.00 | ||
V2S | sec_cm_manuf_state_bkgn_chk | lc_ctrl_state_failure | 42.160s | 377.184us | 50 | 50 | 100.00 |
lc_ctrl_sec_cm | 36.220s | 231.823us | 5 | 5 | 100.00 | ||
V2S | sec_cm_transition_ctr_bkgn_chk | lc_ctrl_state_failure | 42.160s | 377.184us | 50 | 50 | 100.00 |
lc_ctrl_sec_cm | 36.220s | 231.823us | 5 | 5 | 100.00 | ||
V2S | sec_cm_state_config_sparse | lc_ctrl_state_failure | 42.160s | 377.184us | 50 | 50 | 100.00 |
lc_ctrl_sec_cm | 36.220s | 231.823us | 5 | 5 | 100.00 | ||
V2S | sec_cm_main_fsm_sparse | lc_ctrl_state_failure | 42.160s | 377.184us | 50 | 50 | 100.00 |
lc_ctrl_sec_cm | 36.220s | 231.823us | 5 | 5 | 100.00 | ||
V2S | sec_cm_kmac_fsm_sparse | lc_ctrl_state_failure | 42.160s | 377.184us | 50 | 50 | 100.00 |
lc_ctrl_sec_cm | 36.220s | 231.823us | 5 | 5 | 100.00 | ||
V2S | sec_cm_main_fsm_local_esc | lc_ctrl_state_failure | 42.160s | 377.184us | 50 | 50 | 100.00 |
lc_ctrl_sec_cm | 36.220s | 231.823us | 5 | 5 | 100.00 | ||
V2S | sec_cm_main_fsm_global_esc | lc_ctrl_security_escalation | 13.440s | 1.047ms | 50 | 50 | 100.00 |
V2S | sec_cm_main_ctrl_flow_consistency | lc_ctrl_state_post_trans | 10.950s | 156.334us | 50 | 50 | 100.00 |
lc_ctrl_jtag_state_post_trans | 29.700s | 5.759ms | 20 | 20 | 100.00 | ||
V2S | sec_cm_intersig_mubi | lc_ctrl_sec_mubi | 22.080s | 2.190ms | 50 | 50 | 100.00 |
V2S | sec_cm_token_valid_ctrl_mubi | lc_ctrl_sec_mubi | 22.080s | 2.190ms | 50 | 50 | 100.00 |
V2S | sec_cm_token_digest | lc_ctrl_sec_token_digest | 28.650s | 1.168ms | 50 | 50 | 100.00 |
V2S | sec_cm_token_mux_ctrl_redun | lc_ctrl_sec_token_mux | 20.660s | 670.285us | 50 | 50 | 100.00 |
V2S | sec_cm_token_valid_mux_redun | lc_ctrl_sec_token_mux | 20.660s | 670.285us | 50 | 50 | 100.00 |
V2S | TOTAL | 175 | 175 | 100.00 | |||
V3 | stress_all_with_rand_reset | lc_ctrl_stress_all_with_rand_reset | 40.956m | 33.579ms | 27 | 50 | 54.00 |
V3 | TOTAL | 27 | 50 | 54.00 | |||
TOTAL | 1005 | 1030 | 97.57 |
Items | Total | Written | Passing | Progress |
---|---|---|---|---|
V1 | 6 | 6 | 6 | 100.00 |
V2 | 27 | 27 | 26 | 96.30 |
V2S | 5 | 5 | 5 | 100.00 |
V3 | 1 | 1 | 0 | 0.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
---|---|---|---|---|---|---|---|
97.17 | 97.92 | 95.56 | 93.38 | 100.00 | 98.52 | 98.51 | 96.29 |
UVM_ERROR (cip_base_vseq.sv:828) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
has 20 failures:
0.lc_ctrl_stress_all_with_rand_reset.16851972254253411845103787772853209145976516403913969743342927246759265205974
Line 12480, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/0.lc_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 10150836372 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 10150836372 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.lc_ctrl_stress_all_with_rand_reset.109901920998502945959838106199815334110001795611912464072378120697387241773773
Line 7785, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/1.lc_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 111208948744 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 111208948744 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 18 more failures.
Error-[CNST-STOF] Constraint solver timeout failure
has 2 failures:
7.lc_ctrl_stress_all_with_rand_reset.86251127783281238945504760117262917276824895300034545009936986101266055424808
Line 37294, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/7.lc_ctrl_stress_all_with_rand_reset/latest/run.log
Error-[CNST-STOF] Constraint solver timeout failure
../src/lowrisc_dv_sec_cm_0/prim_sparse_fsm_flop_if.sv, 43
Exceeded cpu time limit during solve.
Please use the run-time switch +ntb_solver_cpu_limit to increase the cpu
limit. The default cpu limit is 1000 seconds per partition.
11.lc_ctrl_stress_all_with_rand_reset.3169996678964191927073121343823625001830568701455889906641505349849289017317
Line 42604, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/11.lc_ctrl_stress_all_with_rand_reset/latest/run.log
Error-[CNST-STOF] Constraint solver timeout failure
../src/lowrisc_dv_sec_cm_0/prim_sparse_fsm_flop_if.sv, 43
Exceeded cpu time limit during solve.
Please use the run-time switch +ntb_solver_cpu_limit to increase the cpu
limit. The default cpu limit is 1000 seconds per partition.
UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (* [*] vs * [*])
has 1 failures:
3.lc_ctrl_stress_all.80516590141125074105533232350944000065525564312510636514399922884118821244876
Line 838, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/3.lc_ctrl_stress_all/latest/run.log
UVM_ERROR @ 390548547 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
UVM_INFO @ 390548547 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:554) [lc_ctrl_smoke_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_prog_error fired unexpectedly!
has 1 failures:
18.lc_ctrl_stress_all_with_rand_reset.50346427757936431179127432335044499541876231273834425907460415078007958577271
Line 24829, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/18.lc_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 85231332338 ps: (cip_base_vseq.sv:554) [uvm_test_top.env.virtual_sequencer.lc_ctrl_smoke_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_prog_error fired unexpectedly!
UVM_INFO @ 85231332338 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:301) scoreboard [scoreboard] alert fatal_prog_error did not trigger max_delay:*
has 1 failures:
22.lc_ctrl_stress_all.12366357969530376106427584952233842038379381489625163025852259983288009375504
Line 11576, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/22.lc_ctrl_stress_all/latest/run.log
UVM_ERROR @ 33839692220 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
UVM_INFO @ 33839692220 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---