LC_CTRL/VOLATILE_UNLOCK_DISABLED Simulation Results

Tuesday June 25 2024 23:02:40 UTC

GitHub Revision: 3fd3528c8c

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 44317642457786780768002458033256869318159334982704173107202396839344093642292

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	13.080s	437.259us	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.420s	22.562us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.100s	15.644us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	3.050s	217.501us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	1.460s	24.652us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	2.250s	29.889us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.100s	15.644us	20	20	100.00
		lc_ctrl_csr_aliasing	1.460s	24.652us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	12.590s	60.953us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	26.030s	469.389us	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	0.890s	14.164us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	5.860s	261.699us	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	36.970s	5.462ms	50	50	100.00
V2	lc_errors	lc_ctrl_errors	23.860s	1.129ms	49	50	98.00
V2	security_escalation	lc_ctrl_state_failure	36.970s	5.462ms	50	50	100.00
		lc_ctrl_prog_failure	5.860s	261.699us	50	50	100.00
		lc_ctrl_errors	23.860s	1.129ms	49	50	98.00
		lc_ctrl_security_escalation	17.380s	491.619us	50	50	100.00
		lc_ctrl_jtag_state_failure	2.097m	6.887ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	26.790s	3.984ms	20	20	100.00
		lc_ctrl_jtag_errors	1.947m	18.220ms	19	20	95.00
V2	jtag_access	lc_ctrl_jtag_smoke	15.040s	4.665ms	20	20	100.00
		lc_ctrl_jtag_state_post_trans	27.130s	1.567ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	26.790s	3.984ms	20	20	100.00
		lc_ctrl_jtag_errors	1.947m	18.220ms	19	20	95.00
		lc_ctrl_jtag_access	18.530s	1.760ms	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	28.080s	3.414ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	3.470s	485.471us	10	10	100.00
		lc_ctrl_jtag_csr_rw	3.570s	129.548us	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	38.930s	1.787ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	13.920s	588.752us	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	2.060s	201.436us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	5.760s	190.087us	10	10	100.00
		lc_ctrl_jtag_alert_test	1.810s	45.744us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	15.500s	15.029ms	9	10	90.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.150s	64.383us	50	50	100.00
V2	stress_all	lc_ctrl_stress_all	10.415m	74.089ms	49	50	98.00
V2	alert_test	lc_ctrl_alert_test	1.530s	60.864us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	4.650s	117.390us	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	4.650s	117.390us	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.420s	22.562us	5	5	100.00
		lc_ctrl_csr_rw	1.100s	15.644us	20	20	100.00
		lc_ctrl_csr_aliasing	1.460s	24.652us	5	5	100.00
		lc_ctrl_same_csr_outstanding	2.050s	48.145us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.420s	22.562us	5	5	100.00
		lc_ctrl_csr_rw	1.100s	15.644us	20	20	100.00
		lc_ctrl_csr_aliasing	1.460s	24.652us	5	5	100.00
		lc_ctrl_same_csr_outstanding	2.050s	48.145us	20	20	100.00
V2		TOTAL			696	700	99.43
V2S	tl_intg_err	lc_ctrl_sec_cm	38.710s	229.507us	5	5	100.00
		lc_ctrl_tl_intg_err	4.250s	114.302us	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	4.250s	114.302us	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	26.030s	469.389us	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	36.970s	5.462ms	50	50	100.00
		lc_ctrl_sec_cm	38.710s	229.507us	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	36.970s	5.462ms	50	50	100.00
		lc_ctrl_sec_cm	38.710s	229.507us	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	36.970s	5.462ms	50	50	100.00
		lc_ctrl_sec_cm	38.710s	229.507us	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	36.970s	5.462ms	50	50	100.00
		lc_ctrl_sec_cm	38.710s	229.507us	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	36.970s	5.462ms	50	50	100.00
		lc_ctrl_sec_cm	38.710s	229.507us	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	36.970s	5.462ms	50	50	100.00
		lc_ctrl_sec_cm	38.710s	229.507us	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	36.970s	5.462ms	50	50	100.00
		lc_ctrl_sec_cm	38.710s	229.507us	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	36.970s	5.462ms	50	50	100.00
		lc_ctrl_sec_cm	38.710s	229.507us	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	17.380s	491.619us	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	12.590s	60.953us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	27.130s	1.567ms	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	19.440s	3.579ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	19.440s	3.579ms	50	50	100.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	25.150s	2.875ms	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	20.430s	2.002ms	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	20.430s	2.002ms	50	50	100.00
V2S		TOTAL			175	175	100.00
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	36.963m	262.751ms	23	50	46.00
V3		TOTAL			23	50	46.00
		TOTAL			999	1030	96.99

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	23	85.19
V2S	5	5	5	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.87	97.92	95.84	93.38	97.62	98.52	98.51	96.29

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:828) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 21 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 21 failures.

    • 0.lc_ctrl_stress_all_with_rand_reset.66947174574001439260866829878189454674543876939403071217571052874114517622648
      Line 36879, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/0.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 20811582688 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 20811582688 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 1.lc_ctrl_stress_all_with_rand_reset.46947248437187168542897261965653331746048294416333981864061598426112608849313
      Line 30730, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/1.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 158721887110 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 158721887110 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 19 more failures.

• UVM_ERROR (cip_base_scoreboard.sv:301) scoreboard [scoreboard] alert fatal_prog_error did not trigger max_delay:* has 3 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 3 failures.

    • 8.lc_ctrl_stress_all_with_rand_reset.27671988913987747664872834632670329650503020624287691901151151805664129653239
      Line 25561, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/8.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 40104791595 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 40104791595 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 15.lc_ctrl_stress_all_with_rand_reset.46184053214672370741907533670131050001613196448347539411455809152698133386746
      Line 3663, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/15.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 11274687550 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 11274687550 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 1 more failures.

• UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (* [*] vs * [*]) has 2 failures:

  • Test lc_ctrl_stress_all has 1 failures.

    • 2.lc_ctrl_stress_all.33327264106268865745575115627048593879804319386345101464762434447234619170306
      Line 16296, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/2.lc_ctrl_stress_all/latest/run.log

        UVM_ERROR @ 22961613874 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 22961613874 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test lc_ctrl_errors has 1 failures.

    • 15.lc_ctrl_errors.18590786731572393764848920226565855056469107600835072122895463252448874361383
      Line 338, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/15.lc_ctrl_errors/latest/run.log

        UVM_ERROR @  28027945 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
        UVM_INFO @  28027945 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:554) [lc_ctrl_common_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_state_error fired unexpectedly! has 2 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 2 failures.

    • 9.lc_ctrl_stress_all_with_rand_reset.88295095004843314093900075201625850123262088514788873537497012804218265297843
      Line 26779, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/9.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 49730218686 ps: (cip_base_vseq.sv:554) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
        UVM_INFO @ 49730218686 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 33.lc_ctrl_stress_all_with_rand_reset.14129464945889909818861548120159791692413964477159987725558300898153883497466
      Line 41398, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/33.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 32191622659 ps: (cip_base_vseq.sv:554) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
        UVM_INFO @ 32191622659 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (lc_ctrl_jtag_priority_vseq.sv:113) [lc_ctrl_jtag_priority_vseq] timeout occurred! has 1 failures:

  • Test lc_ctrl_jtag_priority has 1 failures.

    • 7.lc_ctrl_jtag_priority.87503748193255814670060968597943050085256940829074719154317486849409708648970
      Line 427, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/7.lc_ctrl_jtag_priority/latest/run.log

        UVM_FATAL @ 10021837262 ps: (lc_ctrl_jtag_priority_vseq.sv:113) [uvm_test_top.env.virtual_sequencer.lc_ctrl_jtag_priority_vseq] timeout occurred!
        UVM_INFO @ 10021837262 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (lc_ctrl_errors_vseq.sv:769) [lc_ctrl_lc_errors_vseq] Check failed otp_error_act == otp_error_exp (* [*] vs * [*]) has 1 failures:

  • Test lc_ctrl_jtag_errors has 1 failures.

    • 15.lc_ctrl_jtag_errors.27795065803489174747585237572508490164791209836697710158685966932288033108499
      Line 368, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/15.lc_ctrl_jtag_errors/latest/run.log

        UVM_ERROR @  38836592 ps: (lc_ctrl_errors_vseq.sv:769) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed otp_error_act == otp_error_exp (0 [0x0] vs 1 [0x1])
        UVM_INFO @  38836592 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Error-[CNST-STOF] Constraint solver timeout failure has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 25.lc_ctrl_stress_all_with_rand_reset.33790787477621633730071719019330380581021670084026072331617106067922433161490
      Line 41983, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/25.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        Error-[CNST-STOF] Constraint solver timeout failure
        ../src/lowrisc_dv_sec_cm_0/prim_sparse_fsm_flop_if.sv, 43
          Exceeded cpu time limit during solve.
          Please use the run-time switch +ntb_solver_cpu_limit to increase the cpu
          limit.  The default cpu limit is 1000 seconds per partition.
      

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