LC_CTRL/VOLATILE_UNLOCK_DISABLED Simulation Results

Wednesday June 26 2024 23:02:36 UTC

GitHub Revision: be1c4a4f52

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 44766564427213563291105655232733134394512207819884794315335669279596867428010

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	14.680s	1.066ms	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.100s	23.480us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.110s	16.955us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	2.760s	433.750us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	1.770s	153.232us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	1.820s	133.880us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.110s	16.955us	20	20	100.00
		lc_ctrl_csr_aliasing	1.770s	153.232us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	13.270s	188.604us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	20.160s	566.694us	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	0.990s	11.895us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	5.300s	122.332us	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	39.490s	2.063ms	50	50	100.00
V2	lc_errors	lc_ctrl_errors	20.360s	628.584us	49	50	98.00
V2	security_escalation	lc_ctrl_state_failure	39.490s	2.063ms	50	50	100.00
		lc_ctrl_prog_failure	5.300s	122.332us	50	50	100.00
		lc_ctrl_errors	20.360s	628.584us	49	50	98.00
		lc_ctrl_security_escalation	18.680s	1.122ms	50	50	100.00
		lc_ctrl_jtag_state_failure	2.553m	10.007ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	20.830s	8.862ms	20	20	100.00
		lc_ctrl_jtag_errors	2.151m	4.667ms	20	20	100.00
V2	jtag_access	lc_ctrl_jtag_smoke	9.000s	304.456us	20	20	100.00
		lc_ctrl_jtag_state_post_trans	29.060s	4.415ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	20.830s	8.862ms	20	20	100.00
		lc_ctrl_jtag_errors	2.151m	4.667ms	20	20	100.00
		lc_ctrl_jtag_access	18.550s	1.392ms	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	30.410s	3.377ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	3.480s	568.267us	10	10	100.00
		lc_ctrl_jtag_csr_rw	2.360s	64.935us	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	18.400s	695.741us	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	19.540s	1.032ms	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	1.500s	47.841us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	3.370s	477.118us	10	10	100.00
		lc_ctrl_jtag_alert_test	2.550s	85.126us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	15.460s	3.569ms	10	10	100.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.270s	15.514us	50	50	100.00
V2	stress_all	lc_ctrl_stress_all	9.703m	97.073ms	50	50	100.00
V2	alert_test	lc_ctrl_alert_test	1.370s	32.008us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	5.190s	122.465us	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	5.190s	122.465us	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.100s	23.480us	5	5	100.00
		lc_ctrl_csr_rw	1.110s	16.955us	20	20	100.00
		lc_ctrl_csr_aliasing	1.770s	153.232us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.950s	86.904us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.100s	23.480us	5	5	100.00
		lc_ctrl_csr_rw	1.110s	16.955us	20	20	100.00
		lc_ctrl_csr_aliasing	1.770s	153.232us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.950s	86.904us	20	20	100.00
V2		TOTAL			699	700	99.86
V2S	tl_intg_err	lc_ctrl_sec_cm	45.740s	201.368us	5	5	100.00
		lc_ctrl_tl_intg_err	3.790s	182.469us	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	3.790s	182.469us	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	20.160s	566.694us	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	39.490s	2.063ms	50	50	100.00
		lc_ctrl_sec_cm	45.740s	201.368us	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	39.490s	2.063ms	50	50	100.00
		lc_ctrl_sec_cm	45.740s	201.368us	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	39.490s	2.063ms	50	50	100.00
		lc_ctrl_sec_cm	45.740s	201.368us	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	39.490s	2.063ms	50	50	100.00
		lc_ctrl_sec_cm	45.740s	201.368us	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	39.490s	2.063ms	50	50	100.00
		lc_ctrl_sec_cm	45.740s	201.368us	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	39.490s	2.063ms	50	50	100.00
		lc_ctrl_sec_cm	45.740s	201.368us	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	39.490s	2.063ms	50	50	100.00
		lc_ctrl_sec_cm	45.740s	201.368us	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	39.490s	2.063ms	50	50	100.00
		lc_ctrl_sec_cm	45.740s	201.368us	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	18.680s	1.122ms	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	13.270s	188.604us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	29.060s	4.415ms	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	24.410s	1.664ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	24.410s	1.664ms	50	50	100.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	26.430s	1.365ms	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	18.970s	13.598ms	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	18.970s	13.598ms	50	50	100.00
V2S		TOTAL			175	175	100.00
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	1.477h	106.968ms	18	50	36.00
V3		TOTAL			18	50	36.00
		TOTAL			997	1030	96.80

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	26	96.30
V2S	5	5	5	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.18	97.92	95.84	93.38	100.00	98.31	98.51	96.29

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:828) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 30 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 30 failures.

    • 1.lc_ctrl_stress_all_with_rand_reset.103626884481599308238619105105152300747150930127960376228003811760796298926342
      Line 13580, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/1.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 39575675760 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 39575675760 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 2.lc_ctrl_stress_all_with_rand_reset.27083661783725327204864626877018485482749128673845314502028086265295013748183
      Line 14652, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/2.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 51955229235 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 51955229235 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 28 more failures.

• UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (* [*] vs * [*]) has 1 failures:

  • Test lc_ctrl_errors has 1 failures.

    • 25.lc_ctrl_errors.69813809409831107226860946757117941322145372393754140000132293214640464864392
      Line 1347, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/25.lc_ctrl_errors/latest/run.log

        UVM_ERROR @  96296559 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
        UVM_INFO @  96296559 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_scoreboard.sv:301) scoreboard [scoreboard] alert fatal_prog_error did not trigger max_delay:* has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 25.lc_ctrl_stress_all_with_rand_reset.79222054976013447320316875109867191150737007566717345041818564084806801009061
      Line 26074, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/25.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 110158184448 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 110158184448 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:554) [lc_ctrl_common_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_state_error fired unexpectedly! has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 45.lc_ctrl_stress_all_with_rand_reset.52567688137735680169332514675662308002340938861761252647240512739132126228822
      Line 3050, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/45.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 37321295312 ps: (cip_base_vseq.sv:554) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
        UVM_INFO @ 37321295312 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

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