LC_CTRL/VOLATILE_UNLOCK_DISABLED Simulation Results

Thursday June 27 2024 23:02:31 UTC

GitHub Revision: 8db2a18db1

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 100513533386727882033709335126269317053614297947080434367729937568368619502352

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	10.180s	498.280us	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.120s	15.928us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.220s	17.482us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	2.600s	135.452us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	1.620s	32.362us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	2.230s	52.832us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.220s	17.482us	20	20	100.00
		lc_ctrl_csr_aliasing	1.620s	32.362us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	10.360s	278.979us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	13.580s	3.301ms	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	0.990s	12.291us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	5.390s	497.071us	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	37.210s	1.035ms	50	50	100.00
V2	lc_errors	lc_ctrl_errors	27.290s	4.080ms	50	50	100.00
V2	security_escalation	lc_ctrl_state_failure	37.210s	1.035ms	50	50	100.00
		lc_ctrl_prog_failure	5.390s	497.071us	50	50	100.00
		lc_ctrl_errors	27.290s	4.080ms	50	50	100.00
		lc_ctrl_security_escalation	14.490s	368.591us	50	50	100.00
		lc_ctrl_jtag_state_failure	1.933m	12.634ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	24.140s	987.861us	20	20	100.00
		lc_ctrl_jtag_errors	1.481m	21.701ms	19	20	95.00
V2	jtag_access	lc_ctrl_jtag_smoke	15.180s	2.310ms	20	20	100.00
		lc_ctrl_jtag_state_post_trans	39.250s	1.244ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	24.140s	987.861us	20	20	100.00
		lc_ctrl_jtag_errors	1.481m	21.701ms	19	20	95.00
		lc_ctrl_jtag_access	27.430s	1.205ms	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	27.960s	4.006ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	2.630s	162.376us	10	10	100.00
		lc_ctrl_jtag_csr_rw	2.770s	584.280us	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	44.760s	3.967ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	22.460s	1.027ms	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	1.590s	22.027us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	6.560s	281.473us	10	10	100.00
		lc_ctrl_jtag_alert_test	1.740s	171.990us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	29.000s	2.623ms	10	10	100.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.140s	16.222us	50	50	100.00
V2	stress_all	lc_ctrl_stress_all	7.299m	29.248ms	50	50	100.00
V2	alert_test	lc_ctrl_alert_test	1.460s	29.547us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	5.560s	127.383us	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	5.560s	127.383us	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.120s	15.928us	5	5	100.00
		lc_ctrl_csr_rw	1.220s	17.482us	20	20	100.00
		lc_ctrl_csr_aliasing	1.620s	32.362us	5	5	100.00
		lc_ctrl_same_csr_outstanding	2.160s	46.612us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.120s	15.928us	5	5	100.00
		lc_ctrl_csr_rw	1.220s	17.482us	20	20	100.00
		lc_ctrl_csr_aliasing	1.620s	32.362us	5	5	100.00
		lc_ctrl_same_csr_outstanding	2.160s	46.612us	20	20	100.00
V2		TOTAL			699	700	99.86
V2S	tl_intg_err	lc_ctrl_sec_cm	42.130s	204.076us	5	5	100.00
		lc_ctrl_tl_intg_err	4.200s	117.918us	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	4.200s	117.918us	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	13.580s	3.301ms	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	37.210s	1.035ms	50	50	100.00
		lc_ctrl_sec_cm	42.130s	204.076us	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	37.210s	1.035ms	50	50	100.00
		lc_ctrl_sec_cm	42.130s	204.076us	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	37.210s	1.035ms	50	50	100.00
		lc_ctrl_sec_cm	42.130s	204.076us	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	37.210s	1.035ms	50	50	100.00
		lc_ctrl_sec_cm	42.130s	204.076us	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	37.210s	1.035ms	50	50	100.00
		lc_ctrl_sec_cm	42.130s	204.076us	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	37.210s	1.035ms	50	50	100.00
		lc_ctrl_sec_cm	42.130s	204.076us	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	37.210s	1.035ms	50	50	100.00
		lc_ctrl_sec_cm	42.130s	204.076us	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	37.210s	1.035ms	50	50	100.00
		lc_ctrl_sec_cm	42.130s	204.076us	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	14.490s	368.591us	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	10.360s	278.979us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	39.250s	1.244ms	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	23.120s	5.241ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	23.120s	5.241ms	50	50	100.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	24.030s	2.538ms	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	18.940s	502.406us	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	18.940s	502.406us	50	50	100.00
V2S		TOTAL			175	175	100.00
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	30.850m	272.120ms	28	50	56.00
V3		TOTAL			28	50	56.00
		TOTAL			1007	1030	97.77

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	26	96.30
V2S	5	5	5	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.28	97.92	95.93	93.38	100.00	98.52	98.76	96.47

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:828) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 19 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 19 failures.

    • 2.lc_ctrl_stress_all_with_rand_reset.10179115314005112939475130829843539897447968231538536385869500636129464916095
      Line 330, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/2.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1146243915 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 1146243915 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 7.lc_ctrl_stress_all_with_rand_reset.34494401561720060568940254664521504573082972421261014144355569499630013405485
      Line 26243, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/7.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 24690269944 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 24690269944 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 17 more failures.

• UVM_ERROR (cip_base_vseq.sv:554) [lc_ctrl_common_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_state_error fired unexpectedly! has 2 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 2 failures.

    • 9.lc_ctrl_stress_all_with_rand_reset.17551221122210100144389498264427296927098160422887179507367307973057458817610
      Line 28512, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/9.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 55000970948 ps: (cip_base_vseq.sv:554) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
        UVM_INFO @ 55000970948 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 12.lc_ctrl_stress_all_with_rand_reset.59401754649833862143731193465964827491386621489670220880635064095786963570512
      Line 37945, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/12.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 31721579304 ps: (cip_base_vseq.sv:554) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
        UVM_INFO @ 31721579304 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (* [*] vs * [*]) has 1 failures:

  • Test lc_ctrl_jtag_errors has 1 failures.

    • 13.lc_ctrl_jtag_errors.57491315730740202846196984207526305236610582120062794572841270475994488858280
      Line 2689, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/13.lc_ctrl_jtag_errors/latest/run.log

        UVM_ERROR @ 24600535244 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 24600535244 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Error-[CNST-STOF] Constraint solver timeout failure has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 48.lc_ctrl_stress_all_with_rand_reset.29842488478324926833823908780885674100174850331162973587411812707222891782104
      Line 37944, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/48.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        Error-[CNST-STOF] Constraint solver timeout failure
        ../src/lowrisc_dv_sec_cm_0/prim_sparse_fsm_flop_if.sv, 43
          Exceeded cpu time limit during solve.
          Please use the run-time switch +ntb_solver_cpu_limit to increase the cpu
          limit.  The default cpu limit is 1000 seconds per partition.
      

Past Results

• Latest
• 2024.06.27_11.11.42
• 2024.06.26_11.08.33
• 2024.06.25_11.31.26
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