3d5220a43f| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | lc_ctrl_smoke | 10.800s | 185.832us | 49 | 50 | 98.00 |
| V1 | csr_hw_reset | lc_ctrl_csr_hw_reset | 1.110s | 15.044us | 5 | 5 | 100.00 |
| V1 | csr_rw | lc_ctrl_csr_rw | 1.110s | 16.677us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | lc_ctrl_csr_bit_bash | 3.340s | 106.572us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | lc_ctrl_csr_aliasing | 1.180s | 28.066us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | lc_ctrl_csr_mem_rw_with_rand_reset | 1.820s | 201.974us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | lc_ctrl_csr_rw | 1.110s | 16.677us | 20 | 20 | 100.00 |
| lc_ctrl_csr_aliasing | 1.180s | 28.066us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 104 | 105 | 99.05 | |||
| V2 | state_post_trans | lc_ctrl_state_post_trans | 10.330s | 268.527us | 46 | 50 | 92.00 |
| V2 | regwen_during_op | lc_ctrl_regwen_during_op | 19.370s | 1.152ms | 10 | 10 | 100.00 |
| V2 | rand_wr_claim_transition_if | lc_ctrl_claim_transition_if | 0.960s | 11.141us | 10 | 10 | 100.00 |
| V2 | lc_prog_failure | lc_ctrl_prog_failure | 6.190s | 177.164us | 49 | 50 | 98.00 |
| V2 | lc_state_failure | lc_ctrl_state_failure | 36.990s | 656.590us | 48 | 50 | 96.00 |
| V2 | lc_errors | lc_ctrl_errors | 25.360s | 2.979ms | 49 | 50 | 98.00 |
| V2 | security_escalation | lc_ctrl_state_failure | 36.990s | 656.590us | 48 | 50 | 96.00 |
| lc_ctrl_prog_failure | 6.190s | 177.164us | 49 | 50 | 98.00 | ||
| lc_ctrl_errors | 25.360s | 2.979ms | 49 | 50 | 98.00 | ||
| lc_ctrl_security_escalation | 14.330s | 876.748us | 48 | 50 | 96.00 | ||
| lc_ctrl_jtag_state_failure | 1.438m | 8.545ms | 20 | 20 | 100.00 | ||
| lc_ctrl_jtag_prog_failure | 23.520s | 917.843us | 19 | 20 | 95.00 | ||
| lc_ctrl_jtag_errors | 1.432m | 18.051ms | 20 | 20 | 100.00 | ||
| V2 | jtag_access | lc_ctrl_jtag_smoke | 13.210s | 975.210us | 20 | 20 | 100.00 |
| lc_ctrl_jtag_state_post_trans | 34.260s | 17.214ms | 20 | 20 | 100.00 | ||
| lc_ctrl_jtag_prog_failure | 23.520s | 917.843us | 19 | 20 | 95.00 | ||
| lc_ctrl_jtag_errors | 1.432m | 18.051ms | 20 | 20 | 100.00 | ||
| lc_ctrl_jtag_access | 27.170s | 1.138ms | 50 | 50 | 100.00 | ||
| lc_ctrl_jtag_regwen_during_op | 34.100s | 1.147ms | 10 | 10 | 100.00 | ||
| lc_ctrl_jtag_csr_hw_reset | 3.950s | 266.542us | 10 | 10 | 100.00 | ||
| lc_ctrl_jtag_csr_rw | 2.500s | 82.445us | 10 | 10 | 100.00 | ||
| lc_ctrl_jtag_csr_bit_bash | 31.450s | 4.966ms | 10 | 10 | 100.00 | ||
| lc_ctrl_jtag_csr_aliasing | 25.790s | 4.786ms | 10 | 10 | 100.00 | ||
| lc_ctrl_jtag_same_csr_outstanding | 2.010s | 274.628us | 10 | 10 | 100.00 | ||
| lc_ctrl_jtag_csr_mem_rw_with_rand_reset | 6.520s | 2.466ms | 10 | 10 | 100.00 | ||
| lc_ctrl_jtag_alert_test | 2.930s | 102.387us | 10 | 10 | 100.00 | ||
| V2 | jtag_priority | lc_ctrl_jtag_priority | 43.990s | 14.807ms | 10 | 10 | 100.00 |
| V2 | lc_ctrl_volatile_unlock | lc_ctrl_volatile_unlock_smoke | 1.200s | 42.061us | 49 | 50 | 98.00 |
| V2 | stress_all | lc_ctrl_stress_all | 16.414m | 32.702ms | 50 | 50 | 100.00 |
| V2 | alert_test | lc_ctrl_alert_test | 1.400s | 93.482us | 48 | 50 | 96.00 |
| V2 | tl_d_oob_addr_access | lc_ctrl_tl_errors | 4.750s | 139.978us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | lc_ctrl_tl_errors | 4.750s | 139.978us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | lc_ctrl_csr_hw_reset | 1.110s | 15.044us | 5 | 5 | 100.00 |
| lc_ctrl_csr_rw | 1.110s | 16.677us | 20 | 20 | 100.00 | ||
| lc_ctrl_csr_aliasing | 1.180s | 28.066us | 5 | 5 | 100.00 | ||
| lc_ctrl_same_csr_outstanding | 2.110s | 50.383us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | lc_ctrl_csr_hw_reset | 1.110s | 15.044us | 5 | 5 | 100.00 |
| lc_ctrl_csr_rw | 1.110s | 16.677us | 20 | 20 | 100.00 | ||
| lc_ctrl_csr_aliasing | 1.180s | 28.066us | 5 | 5 | 100.00 | ||
| lc_ctrl_same_csr_outstanding | 2.110s | 50.383us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 686 | 700 | 98.00 | |||
| V2S | tl_intg_err | lc_ctrl_sec_cm | 37.780s | 200.661us | 5 | 5 | 100.00 |
| lc_ctrl_tl_intg_err | 4.660s | 402.165us | 20 | 20 | 100.00 | ||
| V2S | sec_cm_bus_integrity | lc_ctrl_tl_intg_err | 4.660s | 402.165us | 20 | 20 | 100.00 |
| V2S | sec_cm_transition_config_regwen | lc_ctrl_regwen_during_op | 19.370s | 1.152ms | 10 | 10 | 100.00 |
| V2S | sec_cm_manuf_state_sparse | lc_ctrl_state_failure | 36.990s | 656.590us | 48 | 50 | 96.00 |
| lc_ctrl_sec_cm | 37.780s | 200.661us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_transition_ctr_sparse | lc_ctrl_state_failure | 36.990s | 656.590us | 48 | 50 | 96.00 |
| lc_ctrl_sec_cm | 37.780s | 200.661us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_manuf_state_bkgn_chk | lc_ctrl_state_failure | 36.990s | 656.590us | 48 | 50 | 96.00 |
| lc_ctrl_sec_cm | 37.780s | 200.661us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_transition_ctr_bkgn_chk | lc_ctrl_state_failure | 36.990s | 656.590us | 48 | 50 | 96.00 |
| lc_ctrl_sec_cm | 37.780s | 200.661us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_state_config_sparse | lc_ctrl_state_failure | 36.990s | 656.590us | 48 | 50 | 96.00 |
| lc_ctrl_sec_cm | 37.780s | 200.661us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_main_fsm_sparse | lc_ctrl_state_failure | 36.990s | 656.590us | 48 | 50 | 96.00 |
| lc_ctrl_sec_cm | 37.780s | 200.661us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_kmac_fsm_sparse | lc_ctrl_state_failure | 36.990s | 656.590us | 48 | 50 | 96.00 |
| lc_ctrl_sec_cm | 37.780s | 200.661us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_main_fsm_local_esc | lc_ctrl_state_failure | 36.990s | 656.590us | 48 | 50 | 96.00 |
| lc_ctrl_sec_cm | 37.780s | 200.661us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_main_fsm_global_esc | lc_ctrl_security_escalation | 14.330s | 876.748us | 48 | 50 | 96.00 |
| V2S | sec_cm_main_ctrl_flow_consistency | lc_ctrl_state_post_trans | 10.330s | 268.527us | 46 | 50 | 92.00 |
| lc_ctrl_jtag_state_post_trans | 34.260s | 17.214ms | 20 | 20 | 100.00 | ||
| V2S | sec_cm_intersig_mubi | lc_ctrl_sec_mubi | 22.920s | 551.523us | 49 | 50 | 98.00 |
| V2S | sec_cm_token_valid_ctrl_mubi | lc_ctrl_sec_mubi | 22.920s | 551.523us | 49 | 50 | 98.00 |
| V2S | sec_cm_token_digest | lc_ctrl_sec_token_digest | 27.380s | 1.024ms | 48 | 50 | 96.00 |
| V2S | sec_cm_token_mux_ctrl_redun | lc_ctrl_sec_token_mux | 23.980s | 3.522ms | 47 | 50 | 94.00 |
| V2S | sec_cm_token_valid_mux_redun | lc_ctrl_sec_token_mux | 23.980s | 3.522ms | 47 | 50 | 94.00 |
| V2S | TOTAL | 169 | 175 | 96.57 | |||
| V3 | stress_all_with_rand_reset | lc_ctrl_stress_all_with_rand_reset | 1.402h | 65.757ms | 25 | 50 | 50.00 |
| V3 | TOTAL | 25 | 50 | 50.00 | |||
| TOTAL | 984 | 1030 | 95.53 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 6 | 6 | 5 | 83.33 |
| V2 | 27 | 27 | 19 | 70.37 |
| V2S | 5 | 5 | 2 | 40.00 |
| V3 | 1 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 96.90 | 97.92 | 95.93 | 93.38 | 97.62 | 98.52 | 99.00 | 95.94 |
UVM_ERROR (cip_base_vseq.sv:828) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 20 failures:
0.lc_ctrl_stress_all_with_rand_reset.903694005880126652942594683880822544140359344276383724933736781248221588150
Line 2267, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/0.lc_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 36179955715 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 36179955715 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.lc_ctrl_stress_all_with_rand_reset.7954775332434440096528685291165554414760634429487751454373055275078123768580
Line 12032, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/1.lc_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 47916520884 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 47916520884 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 18 more failures.
Exit reason: Error: User command failed Job returned non-zero exit code has 20 failures:
Test lc_ctrl_state_post_trans has 3 failures.
16.lc_ctrl_state_post_trans.24167893052889969146280820281480673981492535695573376158803969322075433691874
Log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/16.lc_ctrl_state_post_trans/latest/run.log
[make]: simulate
cd /workspace/16.lc_ctrl_state_post_trans/latest && /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2962713314 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_state_post_trans.2962713314
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jun 28 18:40 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:187: simulate] Error 255
20.lc_ctrl_state_post_trans.32928155192619052536465883142782843861392198852466172683066967831204211138418
Log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/20.lc_ctrl_state_post_trans/latest/run.log
[make]: simulate
cd /workspace/20.lc_ctrl_state_post_trans/latest && /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3526565746 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_state_post_trans.3526565746
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jun 28 18:43 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:187: simulate] Error 255
... and 1 more failures.
Test lc_ctrl_jtag_prog_failure has 1 failures.
16.lc_ctrl_jtag_prog_failure.61909478794468514895669576163577580162203414455843836890068750062231402883730
Log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/16.lc_ctrl_jtag_prog_failure/latest/run.log
[make]: simulate
cd /workspace/16.lc_ctrl_jtag_prog_failure/latest && /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=151300754 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_prog_failure.151300754
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jun 28 18:40 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:187: simulate] Error 255
Test lc_ctrl_sec_token_mux has 3 failures.
16.lc_ctrl_sec_token_mux.90407331782068671360091947877206322202802398968018869112160647230589928366406
Log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/16.lc_ctrl_sec_token_mux/latest/run.log
[make]: simulate
cd /workspace/16.lc_ctrl_sec_token_mux/latest && /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2985451846 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_token_mux.2985451846
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jun 28 18:40 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:187: simulate] Error 255
30.lc_ctrl_sec_token_mux.113393101478057449041320020377519573700005196939648014560766989025222395876496
Log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/30.lc_ctrl_sec_token_mux/latest/run.log
[make]: simulate
cd /workspace/30.lc_ctrl_sec_token_mux/latest && /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3355890832 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_token_mux.3355890832
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jun 28 18:46 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:187: simulate] Error 255
... and 1 more failures.
Test lc_ctrl_state_failure has 2 failures.
23.lc_ctrl_state_failure.102624053223450743807960548788888498123415386526969134030808525165149098917683
Log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/23.lc_ctrl_state_failure/latest/run.log
[make]: simulate
cd /workspace/23.lc_ctrl_state_failure/latest && /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148160307 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_state_failure.148160307
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jun 28 18:43 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:187: simulate] Error 255
30.lc_ctrl_state_failure.78998249964203219193353973551584813258922585686097989753586415687897405472225
Log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/30.lc_ctrl_state_failure/latest/run.log
[make]: simulate
cd /workspace/30.lc_ctrl_state_failure/latest && /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449854945 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_state_failure.449854945
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jun 28 18:46 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:187: simulate] Error 255
Test lc_ctrl_sec_token_digest has 2 failures.
23.lc_ctrl_sec_token_digest.17908741563690043298673692935794999651828766805391733970127269090081384824394
Log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/23.lc_ctrl_sec_token_digest/latest/run.log
[make]: simulate
cd /workspace/23.lc_ctrl_sec_token_digest/latest && /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56753738 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_token_digest.56753738
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jun 28 18:43 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:187: simulate] Error 255
28.lc_ctrl_sec_token_digest.48131955269906271450168554266561900260963954203491688514574286108103007624091
Log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/28.lc_ctrl_sec_token_digest/latest/run.log
[make]: simulate
cd /workspace/28.lc_ctrl_sec_token_digest/latest && /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123979675 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_token_digest.2123979675
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jun 28 18:45 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:187: simulate] Error 255
... and 7 more tests.
UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (* [*] vs * [*]) has 2 failures:
3.lc_ctrl_stress_all_with_rand_reset.79920949830944730732175851787219693760243618217502401053149671456263903931793
Line 48100, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/3.lc_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 15556498052 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
UVM_INFO @ 15556498052 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
49.lc_ctrl_stress_all_with_rand_reset.7911132591300355851872473845840995096089772836432934795689117091093085722808
Line 31191, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/49.lc_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 14540563170 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
UVM_INFO @ 14540563170 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job lc_ctrl_volatile_unlock_disabled-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 2 failures:
Test lc_ctrl_state_post_trans has 1 failures.
26.lc_ctrl_state_post_trans.60036324667452993569707333981014150633830650143808983137501953779626574664871
Log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/26.lc_ctrl_state_post_trans/latest/run.log
Job ID: smart:571f08d5-bc1f-4768-baeb-6e91bed378b7
Test lc_ctrl_prog_failure has 1 failures.
26.lc_ctrl_prog_failure.63018680866512673753897197723718376830846916681986008975006193182016796955584
Log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/26.lc_ctrl_prog_failure/latest/run.log
Job ID: smart:6b9ad05b-5bd9-486c-a011-e7ffd2a0aeb0
Error-[CNST-STOF] Constraint solver timeout failure has 1 failures:
2.lc_ctrl_stress_all_with_rand_reset.24713709360223885442177214523869036297720658679321209188775174144345177643515
Line 24347, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/2.lc_ctrl_stress_all_with_rand_reset/latest/run.log
Error-[CNST-STOF] Constraint solver timeout failure
../src/lowrisc_dv_sec_cm_0/prim_sparse_fsm_flop_if.sv, 43
Exceeded cpu time limit during solve.
Please use the run-time switch +ntb_solver_cpu_limit to increase the cpu
limit. The default cpu limit is 1000 seconds per partition.
UVM_ERROR (cip_base_scoreboard.sv:301) scoreboard [scoreboard] alert fatal_prog_error did not trigger max_delay:* has 1 failures:
40.lc_ctrl_stress_all_with_rand_reset.24248025767966591543390199883322545074460296909445043717108562613857910451560
Line 31175, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/40.lc_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 18235277833 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
UVM_INFO @ 18235277833 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---