LC_CTRL/VOLATILE_UNLOCK_DISABLED Simulation Results

Saturday June 29 2024 23:02:35 UTC

GitHub Revision: b33f0bcb4a

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 9407974028806500767465982655187958599819354731549473124644158596869486113221

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	10.520s	1.273ms	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.090s	37.405us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.120s	60.258us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	2.760s	257.085us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	1.850s	38.460us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	2.320s	111.526us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.120s	60.258us	20	20	100.00
		lc_ctrl_csr_aliasing	1.850s	38.460us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	10.040s	555.313us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	20.550s	316.335us	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	0.990s	12.470us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	4.760s	430.259us	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	37.480s	238.196us	50	50	100.00
V2	lc_errors	lc_ctrl_errors	24.950s	711.198us	50	50	100.00
V2	security_escalation	lc_ctrl_state_failure	37.480s	238.196us	50	50	100.00
		lc_ctrl_prog_failure	4.760s	430.259us	50	50	100.00
		lc_ctrl_errors	24.950s	711.198us	50	50	100.00
		lc_ctrl_security_escalation	15.820s	403.062us	50	50	100.00
		lc_ctrl_jtag_state_failure	1.500m	8.598ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	17.290s	1.275ms	20	20	100.00
		lc_ctrl_jtag_errors	1.653m	3.648ms	20	20	100.00
V2	jtag_access	lc_ctrl_jtag_smoke	14.190s	568.385us	20	20	100.00
		lc_ctrl_jtag_state_post_trans	21.030s	2.132ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	17.290s	1.275ms	20	20	100.00
		lc_ctrl_jtag_errors	1.653m	3.648ms	20	20	100.00
		lc_ctrl_jtag_access	27.470s	11.769ms	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	35.720s	2.539ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	3.490s	254.023us	10	10	100.00
		lc_ctrl_jtag_csr_rw	2.090s	55.476us	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	35.630s	6.177ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	20.490s	3.491ms	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	1.560s	51.764us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	4.370s	626.675us	10	10	100.00
		lc_ctrl_jtag_alert_test	3.200s	804.161us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	56.940s	10.003ms	9	10	90.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.090s	13.830us	50	50	100.00
V2	stress_all	lc_ctrl_stress_all	7.262m	48.315ms	47	50	94.00
V2	alert_test	lc_ctrl_alert_test	1.240s	38.347us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	5.370s	202.942us	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	5.370s	202.942us	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.090s	37.405us	5	5	100.00
		lc_ctrl_csr_rw	1.120s	60.258us	20	20	100.00
		lc_ctrl_csr_aliasing	1.850s	38.460us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.990s	49.033us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.090s	37.405us	5	5	100.00
		lc_ctrl_csr_rw	1.120s	60.258us	20	20	100.00
		lc_ctrl_csr_aliasing	1.850s	38.460us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.990s	49.033us	20	20	100.00
V2		TOTAL			696	700	99.43
V2S	tl_intg_err	lc_ctrl_sec_cm	39.640s	237.745us	5	5	100.00
		lc_ctrl_tl_intg_err	7.040s	1.035ms	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	7.040s	1.035ms	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	20.550s	316.335us	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	37.480s	238.196us	50	50	100.00
		lc_ctrl_sec_cm	39.640s	237.745us	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	37.480s	238.196us	50	50	100.00
		lc_ctrl_sec_cm	39.640s	237.745us	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	37.480s	238.196us	50	50	100.00
		lc_ctrl_sec_cm	39.640s	237.745us	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	37.480s	238.196us	50	50	100.00
		lc_ctrl_sec_cm	39.640s	237.745us	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	37.480s	238.196us	50	50	100.00
		lc_ctrl_sec_cm	39.640s	237.745us	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	37.480s	238.196us	50	50	100.00
		lc_ctrl_sec_cm	39.640s	237.745us	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	37.480s	238.196us	50	50	100.00
		lc_ctrl_sec_cm	39.640s	237.745us	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	37.480s	238.196us	50	50	100.00
		lc_ctrl_sec_cm	39.640s	237.745us	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	15.820s	403.062us	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	10.040s	555.313us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	21.030s	2.132ms	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	19.640s	813.209us	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	19.640s	813.209us	50	50	100.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	26.160s	16.755ms	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	14.680s	1.609ms	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	14.680s	1.609ms	50	50	100.00
V2S		TOTAL			175	175	100.00
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	2.033h	136.164ms	24	50	48.00
V3		TOTAL			24	50	48.00
		TOTAL			1000	1030	97.09

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	25	92.59
V2S	5	5	5	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.98	97.92	96.12	93.38	97.62	98.52	99.00	96.29

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:828) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 23 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 23 failures.

    • 0.lc_ctrl_stress_all_with_rand_reset.114444420051106127774863212518094930015329556764914274437078093675135693855073
      Line 16363, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/0.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 34069211317 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 34069211317 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 2.lc_ctrl_stress_all_with_rand_reset.10162719844084747322787052018765646690289427507166909665096514779923474945335
      Line 2935, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/2.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 2458752307 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 2458752307 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 21 more failures.

• UVM_ERROR (cip_base_scoreboard.sv:301) scoreboard [scoreboard] alert fatal_prog_error did not trigger max_delay:* has 3 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 1.lc_ctrl_stress_all_with_rand_reset.97649212564597272695916950175543121812317202264451197395203278303543348401513
      Line 20290, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/1.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 104891544652 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 104891544652 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test lc_ctrl_stress_all has 2 failures.

    • 16.lc_ctrl_stress_all.50916587851032524893017771537172652626115459872871010998272279478327836644694
      Line 7567, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/16.lc_ctrl_stress_all/latest/run.log

        UVM_ERROR @ 13245581600 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 13245581600 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 34.lc_ctrl_stress_all.55659604298369565446153047408131409451467754016684798044539050545171849143142
      Line 7480, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/34.lc_ctrl_stress_all/latest/run.log

        UVM_ERROR @ 10248469685 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 10248469685 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:554) [lc_ctrl_common_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_state_error fired unexpectedly! has 2 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 2 failures.

    • 42.lc_ctrl_stress_all_with_rand_reset.63143748901405841433223704673903066006463914107383270623302474031500783394642
      Line 43933, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/42.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 134306312126 ps: (cip_base_vseq.sv:554) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
        UVM_INFO @ 134306312126 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 44.lc_ctrl_stress_all_with_rand_reset.99866743017542261527233116596384086017954435978693588366281969856414096617585
      Line 63788, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/44.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 197424663305 ps: (cip_base_vseq.sv:554) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
        UVM_INFO @ 197424663305 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (lc_ctrl_jtag_priority_vseq.sv:113) [lc_ctrl_jtag_priority_vseq] timeout occurred! has 1 failures:

  • Test lc_ctrl_jtag_priority has 1 failures.

    • 2.lc_ctrl_jtag_priority.26468824931903035086330324862362120914219081700471629995853044901007310181593
      Line 727, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/2.lc_ctrl_jtag_priority/latest/run.log

        UVM_FATAL @ 10003365360 ps: (lc_ctrl_jtag_priority_vseq.sv:113) [uvm_test_top.env.virtual_sequencer.lc_ctrl_jtag_priority_vseq] timeout occurred!
        UVM_INFO @ 10003365360 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (* [*] vs * [*]) has 1 failures:

  • Test lc_ctrl_stress_all has 1 failures.

    • 37.lc_ctrl_stress_all.21817204179139823615957748860701038692493336017326209235126889702175299426317
      Line 13581, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/37.lc_ctrl_stress_all/latest/run.log

        UVM_ERROR @ 9406485076 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 9406485076 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

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