LC_CTRL/VOLATILE_UNLOCK_DISABLED Simulation Results

Sunday June 30 2024 23:02:20 UTC

GitHub Revision: b33f0bcb4a

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 105302396297609026156504164956156290718642058150905320202190590799028860124396

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	8.640s	813.495us	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.250s	34.292us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.120s	16.499us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	1.810s	112.900us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	1.380s	32.874us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	2.030s	26.993us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.120s	16.499us	20	20	100.00
		lc_ctrl_csr_aliasing	1.380s	32.874us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	12.060s	245.659us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	21.210s	579.383us	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	1.010s	12.059us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	5.300s	508.790us	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	40.830s	345.409us	50	50	100.00
V2	lc_errors	lc_ctrl_errors	24.970s	13.854ms	49	50	98.00
V2	security_escalation	lc_ctrl_state_failure	40.830s	345.409us	50	50	100.00
		lc_ctrl_prog_failure	5.300s	508.790us	50	50	100.00
		lc_ctrl_errors	24.970s	13.854ms	49	50	98.00
		lc_ctrl_security_escalation	15.280s	984.125us	50	50	100.00
		lc_ctrl_jtag_state_failure	1.835m	3.292ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	21.870s	815.057us	20	20	100.00
		lc_ctrl_jtag_errors	1.433m	11.834ms	20	20	100.00
V2	jtag_access	lc_ctrl_jtag_smoke	9.450s	1.315ms	20	20	100.00
		lc_ctrl_jtag_state_post_trans	34.270s	3.791ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	21.870s	815.057us	20	20	100.00
		lc_ctrl_jtag_errors	1.433m	11.834ms	20	20	100.00
		lc_ctrl_jtag_access	23.800s	1.055ms	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	37.990s	2.534ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	3.960s	149.349us	10	10	100.00
		lc_ctrl_jtag_csr_rw	3.820s	269.026us	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	44.920s	2.061ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	10.860s	1.541ms	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	2.090s	50.385us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	7.350s	505.080us	10	10	100.00
		lc_ctrl_jtag_alert_test	2.540s	312.915us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	29.770s	21.786ms	10	10	100.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.150s	13.373us	50	50	100.00
V2	stress_all	lc_ctrl_stress_all	10.934m	69.767ms	50	50	100.00
V2	alert_test	lc_ctrl_alert_test	1.940s	88.492us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	5.940s	592.832us	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	5.940s	592.832us	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.250s	34.292us	5	5	100.00
		lc_ctrl_csr_rw	1.120s	16.499us	20	20	100.00
		lc_ctrl_csr_aliasing	1.380s	32.874us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.980s	580.371us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.250s	34.292us	5	5	100.00
		lc_ctrl_csr_rw	1.120s	16.499us	20	20	100.00
		lc_ctrl_csr_aliasing	1.380s	32.874us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.980s	580.371us	20	20	100.00
V2		TOTAL			699	700	99.86
V2S	tl_intg_err	lc_ctrl_sec_cm	38.470s	222.799us	5	5	100.00
		lc_ctrl_tl_intg_err	4.620s	496.541us	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	4.620s	496.541us	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	21.210s	579.383us	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	40.830s	345.409us	50	50	100.00
		lc_ctrl_sec_cm	38.470s	222.799us	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	40.830s	345.409us	50	50	100.00
		lc_ctrl_sec_cm	38.470s	222.799us	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	40.830s	345.409us	50	50	100.00
		lc_ctrl_sec_cm	38.470s	222.799us	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	40.830s	345.409us	50	50	100.00
		lc_ctrl_sec_cm	38.470s	222.799us	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	40.830s	345.409us	50	50	100.00
		lc_ctrl_sec_cm	38.470s	222.799us	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	40.830s	345.409us	50	50	100.00
		lc_ctrl_sec_cm	38.470s	222.799us	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	40.830s	345.409us	50	50	100.00
		lc_ctrl_sec_cm	38.470s	222.799us	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	40.830s	345.409us	50	50	100.00
		lc_ctrl_sec_cm	38.470s	222.799us	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	15.280s	984.125us	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	12.060s	245.659us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	34.270s	3.791ms	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	24.570s	947.658us	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	24.570s	947.658us	50	50	100.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	24.120s	4.431ms	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	16.060s	3.436ms	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	16.060s	3.436ms	50	50	100.00
V2S		TOTAL			175	175	100.00
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	48.437m	107.898ms	15	50	30.00
V3		TOTAL			15	50	30.00
		TOTAL			994	1030	96.50

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	26	96.30
V2S	5	5	5	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.87	97.92	95.84	93.38	97.62	98.52	98.51	96.29

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:828) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 29 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 29 failures.

    • 0.lc_ctrl_stress_all_with_rand_reset.11660815609190059122217237719029026574934576637847293401697273701038393623338
      Line 30790, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/0.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 50863706957 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 50863706957 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 1.lc_ctrl_stress_all_with_rand_reset.58096697797978700461501133709991617100538699343368688196865974066364758576028
      Line 7338, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/1.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 29699134810 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 29699134810 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 27 more failures.

• UVM_ERROR (cip_base_scoreboard.sv:301) scoreboard [scoreboard] alert fatal_prog_error did not trigger max_delay:* has 3 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 3 failures.

    • 25.lc_ctrl_stress_all_with_rand_reset.36835480834430231402897347017466934296308989918832881079335071302107155293712
      Line 19145, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/25.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 57976424666 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 57976424666 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 34.lc_ctrl_stress_all_with_rand_reset.6326865513642599622245624701233146663721817169352260588965846305290128355932
      Line 31717, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/34.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 120830163057 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 120830163057 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 1 more failures.

• Error-[CNST-STOF] Constraint solver timeout failure has 2 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 2 failures.

    • 18.lc_ctrl_stress_all_with_rand_reset.37178458837787248817436605731148865740672388341163719419625152829579555091264
      Line 44405, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/18.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        Error-[CNST-STOF] Constraint solver timeout failure
        ../src/lowrisc_dv_sec_cm_0/prim_sparse_fsm_flop_if.sv, 43
          Exceeded cpu time limit during solve.
          Please use the run-time switch +ntb_solver_cpu_limit to increase the cpu
          limit.  The default cpu limit is 1000 seconds per partition.
      

    • 27.lc_ctrl_stress_all_with_rand_reset.14964281338913055015674316347271988010559087349811479743447140830820127143548
      Line 31793, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/27.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        Error-[CNST-STOF] Constraint solver timeout failure
        ../src/lowrisc_dv_sec_cm_0/prim_sparse_fsm_flop_if.sv, 43
          Exceeded cpu time limit during solve.
          Please use the run-time switch +ntb_solver_cpu_limit to increase the cpu
          limit.  The default cpu limit is 1000 seconds per partition.
      

• UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (* [*] vs * [*]) has 1 failures:

  • Test lc_ctrl_errors has 1 failures.

    • 5.lc_ctrl_errors.90706444977720667932859822120709434968937002582967173402320399946856777852549
      Line 381, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/5.lc_ctrl_errors/latest/run.log

        UVM_ERROR @   8821849 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
        UVM_INFO @   8821849 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:554) [lc_ctrl_common_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_state_error fired unexpectedly! has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 30.lc_ctrl_stress_all_with_rand_reset.77585728683272164137701612502493079046156631796295736635912820721815408656599
      Line 43086, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/30.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 25464638819 ps: (cip_base_vseq.sv:554) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
        UVM_INFO @ 25464638819 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

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