LC_CTRL/VOLATILE_UNLOCK_DISABLED Simulation Results

Monday July 01 2024 17:07:21 UTC

GitHub Revision: eb56ef55d0

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 287373712151371957859909226915296476629077008125381265920192201371239303276

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	5.950s	432.417us	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.190s	53.734us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.050s	17.061us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	3.090s	355.581us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	1.680s	237.745us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	2.110s	94.451us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.050s	17.061us	20	20	100.00
		lc_ctrl_csr_aliasing	1.680s	237.745us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	10.960s	134.618us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	23.360s	357.699us	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	1.000s	11.255us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	4.320s	1.226ms	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	32.930s	1.302ms	50	50	100.00
V2	lc_errors	lc_ctrl_errors	20.880s	2.202ms	49	50	98.00
V2	security_escalation	lc_ctrl_state_failure	32.930s	1.302ms	50	50	100.00
		lc_ctrl_prog_failure	4.320s	1.226ms	50	50	100.00
		lc_ctrl_errors	20.880s	2.202ms	49	50	98.00
		lc_ctrl_security_escalation	14.420s	420.289us	50	50	100.00
		lc_ctrl_jtag_state_failure	2.351m	4.366ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	19.660s	2.529ms	20	20	100.00
		lc_ctrl_jtag_errors	1.196m	11.143ms	20	20	100.00
V2	jtag_access	lc_ctrl_jtag_smoke	17.670s	727.926us	20	20	100.00
		lc_ctrl_jtag_state_post_trans	32.770s	12.700ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	19.660s	2.529ms	20	20	100.00
		lc_ctrl_jtag_errors	1.196m	11.143ms	20	20	100.00
		lc_ctrl_jtag_access	31.990s	4.786ms	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	39.010s	1.494ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	6.150s	919.647us	10	10	100.00
		lc_ctrl_jtag_csr_rw	4.030s	646.627us	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	36.040s	1.785ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	27.820s	5.298ms	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	2.180s	51.247us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	4.020s	286.060us	10	10	100.00
		lc_ctrl_jtag_alert_test	2.540s	84.278us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	28.830s	5.545ms	10	10	100.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.200s	21.712us	50	50	100.00
V2	stress_all	lc_ctrl_stress_all	11.208m	90.361ms	50	50	100.00
V2	alert_test	lc_ctrl_alert_test	1.270s	20.693us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	6.400s	247.827us	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	6.400s	247.827us	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.190s	53.734us	5	5	100.00
		lc_ctrl_csr_rw	1.050s	17.061us	20	20	100.00
		lc_ctrl_csr_aliasing	1.680s	237.745us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.990s	48.559us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.190s	53.734us	5	5	100.00
		lc_ctrl_csr_rw	1.050s	17.061us	20	20	100.00
		lc_ctrl_csr_aliasing	1.680s	237.745us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.990s	48.559us	20	20	100.00
V2		TOTAL			699	700	99.86
V2S	tl_intg_err	lc_ctrl_sec_cm	38.800s	210.846us	5	5	100.00
		lc_ctrl_tl_intg_err	4.030s	360.725us	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	4.030s	360.725us	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	23.360s	357.699us	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	32.930s	1.302ms	50	50	100.00
		lc_ctrl_sec_cm	38.800s	210.846us	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	32.930s	1.302ms	50	50	100.00
		lc_ctrl_sec_cm	38.800s	210.846us	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	32.930s	1.302ms	50	50	100.00
		lc_ctrl_sec_cm	38.800s	210.846us	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	32.930s	1.302ms	50	50	100.00
		lc_ctrl_sec_cm	38.800s	210.846us	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	32.930s	1.302ms	50	50	100.00
		lc_ctrl_sec_cm	38.800s	210.846us	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	32.930s	1.302ms	50	50	100.00
		lc_ctrl_sec_cm	38.800s	210.846us	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	32.930s	1.302ms	50	50	100.00
		lc_ctrl_sec_cm	38.800s	210.846us	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	32.930s	1.302ms	50	50	100.00
		lc_ctrl_sec_cm	38.800s	210.846us	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	14.420s	420.289us	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	10.960s	134.618us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	32.770s	12.700ms	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	26.310s	710.761us	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	26.310s	710.761us	50	50	100.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	20.230s	715.805us	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	18.370s	501.139us	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	18.370s	501.139us	50	50	100.00
V2S		TOTAL			175	175	100.00
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	20.365m	34.042ms	24	50	48.00
V3		TOTAL			24	50	48.00
		TOTAL			1003	1030	97.38

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	26	96.30
V2S	5	5	5	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.87	97.92	95.66	93.38	97.62	98.52	98.51	96.47

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:828) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 22 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 22 failures.

    • 0.lc_ctrl_stress_all_with_rand_reset.31602163754939815826664619507148889927669599915228864149612285515395129633457
      Line 7944, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/0.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 76296818073 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 76296818073 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 5.lc_ctrl_stress_all_with_rand_reset.67297398360381905238941376669754969030788319957173549027206402785857127240618
      Line 25926, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/5.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 32081376087 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 32081376087 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 20 more failures.

• UVM_ERROR (cip_base_vseq.sv:554) [lc_ctrl_common_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_state_error fired unexpectedly! has 2 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 2 failures.

    • 7.lc_ctrl_stress_all_with_rand_reset.44233883347079271150172668062574672546265353259634572576910226809771048086105
      Line 24010, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/7.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 308791613593 ps: (cip_base_vseq.sv:554) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
        UVM_INFO @ 308791613593 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 30.lc_ctrl_stress_all_with_rand_reset.18255708119250214059298557715769541753377901122357759389769849778915477889102
      Line 17644, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/30.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 62496236819 ps: (cip_base_vseq.sv:554) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
        UVM_INFO @ 62496236819 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Job lc_ctrl_volatile_unlock_disabled-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 26.lc_ctrl_stress_all_with_rand_reset.30454659135099132304118787058155465487045409740599711134667521186194810344946
      Log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/26.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        Job ID: smart:e830b3c9-4ade-4567-bf32-d45b041c6c27
      

• UVM_ERROR (cip_base_vseq.sv:554) [lc_ctrl_regwen_during_op_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_prog_error fired unexpectedly! has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 39.lc_ctrl_stress_all_with_rand_reset.106460514603014204113467090518805325505096289885947660839582243741421314962218
      Line 21778, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/39.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 24200233792 ps: (cip_base_vseq.sv:554) [uvm_test_top.env.virtual_sequencer.lc_ctrl_regwen_during_op_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_prog_error fired unexpectedly!
        UVM_INFO @ 24200233792 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (* [*] vs * [*]) has 1 failures:

  • Test lc_ctrl_errors has 1 failures.

    • 40.lc_ctrl_errors.39653450510421318496269642459831542572953787674972802128275972445657200362480
      Line 1257, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/40.lc_ctrl_errors/latest/run.log

        UVM_ERROR @ 327178549 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 327178549 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

• Latest
• 2024.07.01_10.59.33
• 2024.06.30_11.13.55
• 2024.06.29_09.37.35
• 2024.06.28_11.54.21
• 2024.06.27_11.11.42
• 2024.06.26_11.08.33
• 2024.06.25_11.31.26