LC_CTRL/VOLATILE_UNLOCK_DISABLED Simulation Results

Monday July 01 2024 23:02:26 UTC

GitHub Revision: e9ae10fb42

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 81071883735317974084005537723499931298658500385730214730015283368929474034200

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	10.390s	154.198us	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.130s	96.219us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.180s	18.178us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	2.030s	46.269us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	1.680s	149.078us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	1.900s	101.769us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.180s	18.178us	20	20	100.00
		lc_ctrl_csr_aliasing	1.680s	149.078us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	10.370s	504.193us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	23.680s	688.888us	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	1.040s	14.180us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	5.810s	155.630us	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	37.610s	972.476us	50	50	100.00
V2	lc_errors	lc_ctrl_errors	28.360s	687.725us	49	50	98.00
V2	security_escalation	lc_ctrl_state_failure	37.610s	972.476us	50	50	100.00
		lc_ctrl_prog_failure	5.810s	155.630us	50	50	100.00
		lc_ctrl_errors	28.360s	687.725us	49	50	98.00
		lc_ctrl_security_escalation	18.390s	583.102us	50	50	100.00
		lc_ctrl_jtag_state_failure	1.215m	2.039ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	22.520s	1.733ms	20	20	100.00
		lc_ctrl_jtag_errors	1.424m	12.569ms	20	20	100.00
V2	jtag_access	lc_ctrl_jtag_smoke	10.570s	1.266ms	20	20	100.00
		lc_ctrl_jtag_state_post_trans	26.570s	3.402ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	22.520s	1.733ms	20	20	100.00
		lc_ctrl_jtag_errors	1.424m	12.569ms	20	20	100.00
		lc_ctrl_jtag_access	28.480s	4.912ms	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	35.300s	1.818ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	4.690s	271.105us	10	10	100.00
		lc_ctrl_jtag_csr_rw	3.940s	1.798ms	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	27.050s	4.266ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	20.770s	948.282us	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	2.140s	47.629us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	2.810s	151.891us	10	10	100.00
		lc_ctrl_jtag_alert_test	2.210s	139.549us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	1.179m	3.078ms	10	10	100.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.340s	24.235us	50	50	100.00
V2	stress_all	lc_ctrl_stress_all	6.756m	61.209ms	49	50	98.00
V2	alert_test	lc_ctrl_alert_test	1.320s	25.661us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	6.200s	720.080us	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	6.200s	720.080us	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.130s	96.219us	5	5	100.00
		lc_ctrl_csr_rw	1.180s	18.178us	20	20	100.00
		lc_ctrl_csr_aliasing	1.680s	149.078us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.910s	343.478us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.130s	96.219us	5	5	100.00
		lc_ctrl_csr_rw	1.180s	18.178us	20	20	100.00
		lc_ctrl_csr_aliasing	1.680s	149.078us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.910s	343.478us	20	20	100.00
V2		TOTAL			698	700	99.71
V2S	tl_intg_err	lc_ctrl_sec_cm	43.740s	993.807us	5	5	100.00
		lc_ctrl_tl_intg_err	4.560s	532.128us	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	4.560s	532.128us	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	23.680s	688.888us	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	37.610s	972.476us	50	50	100.00
		lc_ctrl_sec_cm	43.740s	993.807us	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	37.610s	972.476us	50	50	100.00
		lc_ctrl_sec_cm	43.740s	993.807us	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	37.610s	972.476us	50	50	100.00
		lc_ctrl_sec_cm	43.740s	993.807us	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	37.610s	972.476us	50	50	100.00
		lc_ctrl_sec_cm	43.740s	993.807us	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	37.610s	972.476us	50	50	100.00
		lc_ctrl_sec_cm	43.740s	993.807us	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	37.610s	972.476us	50	50	100.00
		lc_ctrl_sec_cm	43.740s	993.807us	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	37.610s	972.476us	50	50	100.00
		lc_ctrl_sec_cm	43.740s	993.807us	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	37.610s	972.476us	50	50	100.00
		lc_ctrl_sec_cm	43.740s	993.807us	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	18.390s	583.102us	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	10.370s	504.193us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	26.570s	3.402ms	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	21.170s	1.729ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	21.170s	1.729ms	50	50	100.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	22.710s	1.604ms	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	25.520s	800.684us	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	25.520s	800.684us	50	50	100.00
V2S		TOTAL			175	175	100.00
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	1.429h	147.092ms	30	50	60.00
V3		TOTAL			30	50	60.00
		TOTAL			1008	1030	97.86

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	25	92.59
V2S	5	5	5	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.34	97.92	96.12	93.38	100.00	98.52	99.00	96.47

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:828) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 17 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 17 failures.

    • 0.lc_ctrl_stress_all_with_rand_reset.3086108623416302370882779212774525352783782111553000040724226289213704448130
      Line 21963, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/0.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 25265840436 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 25265840436 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 2.lc_ctrl_stress_all_with_rand_reset.100567911978019673950935098948083716016981442583120987019424622920936092057216
      Line 24980, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/2.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 20998478996 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 20998478996 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 15 more failures.

• UVM_ERROR (cip_base_vseq.sv:554) [lc_ctrl_common_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_state_error fired unexpectedly! has 2 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 2 failures.

    • 13.lc_ctrl_stress_all_with_rand_reset.77576086129302113016750793165025107987437302775077672575648553545329508711195
      Line 24198, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/13.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 13659596935 ps: (cip_base_vseq.sv:554) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
        UVM_INFO @ 13659596935 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 46.lc_ctrl_stress_all_with_rand_reset.10005724949675245795742395135489855314673977313150596694013470374006717517601
      Line 24169, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/46.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 82735209892 ps: (cip_base_vseq.sv:554) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
        UVM_INFO @ 82735209892 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (* [*] vs * [*]) has 2 failures:

  • Test lc_ctrl_errors has 1 failures.

    • 27.lc_ctrl_errors.7334491583325721912028987740069461747734091827107496631998295845347000583726
      Line 2500, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/27.lc_ctrl_errors/latest/run.log

        UVM_ERROR @ 422310066 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 422310066 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 29.lc_ctrl_stress_all_with_rand_reset.98268080818669920172090008826617274863450446872321616830912438407192446031652
      Line 51338, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/29.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 82319624738 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 82319624738 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_scoreboard.sv:301) scoreboard [scoreboard] alert fatal_prog_error did not trigger max_delay:* has 1 failures:

  • Test lc_ctrl_stress_all has 1 failures.

    • 9.lc_ctrl_stress_all.44632110435633214440720943934292793699350434934139909594603022746377755142698
      Line 5875, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/9.lc_ctrl_stress_all/latest/run.log

        UVM_ERROR @ 32708518640 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 32708518640 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

• Latest
• 2024.07.02_04.15.00
• 2024.07.01_10.59.33
• 2024.06.30_11.13.55
• 2024.06.29_09.37.35
• 2024.06.28_11.54.21
• 2024.06.27_11.11.42
• 2024.06.26_11.08.33