LC_CTRL/VOLATILE_UNLOCK_DISABLED Simulation Results

Tuesday July 02 2024 14:17:13 UTC

GitHub Revision: abd7ce57f2

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 7120396591488306882161367642496372905152431708445539866860566607772054886363

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	5.980s	267.638us	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.340s	23.956us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.100s	12.763us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	2.600s	241.523us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	1.650s	93.815us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	2.110s	29.756us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.100s	12.763us	20	20	100.00
		lc_ctrl_csr_aliasing	1.650s	93.815us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	11.630s	128.643us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	22.840s	613.341us	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	1.050s	15.152us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	5.000s	1.957ms	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	35.870s	3.457ms	50	50	100.00
V2	lc_errors	lc_ctrl_errors	24.480s	2.573ms	49	50	98.00
V2	security_escalation	lc_ctrl_state_failure	35.870s	3.457ms	50	50	100.00
		lc_ctrl_prog_failure	5.000s	1.957ms	50	50	100.00
		lc_ctrl_errors	24.480s	2.573ms	49	50	98.00
		lc_ctrl_security_escalation	16.530s	709.825us	50	50	100.00
		lc_ctrl_jtag_state_failure	1.536m	5.215ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	16.470s	4.624ms	20	20	100.00
		lc_ctrl_jtag_errors	1.820m	4.146ms	20	20	100.00
V2	jtag_access	lc_ctrl_jtag_smoke	8.360s	309.233us	20	20	100.00
		lc_ctrl_jtag_state_post_trans	32.940s	9.528ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	16.470s	4.624ms	20	20	100.00
		lc_ctrl_jtag_errors	1.820m	4.146ms	20	20	100.00
		lc_ctrl_jtag_access	28.250s	2.558ms	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	28.000s	961.083us	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	3.800s	267.559us	10	10	100.00
		lc_ctrl_jtag_csr_rw	3.250s	904.528us	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	49.570s	4.829ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	13.490s	1.101ms	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	1.890s	82.556us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	6.110s	458.953us	10	10	100.00
		lc_ctrl_jtag_alert_test	2.570s	77.222us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	37.760s	3.253ms	10	10	100.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.080s	15.005us	50	50	100.00
V2	stress_all	lc_ctrl_stress_all	9.446m	19.117ms	50	50	100.00
V2	alert_test	lc_ctrl_alert_test	1.610s	43.133us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	4.750s	124.758us	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	4.750s	124.758us	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.340s	23.956us	5	5	100.00
		lc_ctrl_csr_rw	1.100s	12.763us	20	20	100.00
		lc_ctrl_csr_aliasing	1.650s	93.815us	5	5	100.00
		lc_ctrl_same_csr_outstanding	2.050s	163.472us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.340s	23.956us	5	5	100.00
		lc_ctrl_csr_rw	1.100s	12.763us	20	20	100.00
		lc_ctrl_csr_aliasing	1.650s	93.815us	5	5	100.00
		lc_ctrl_same_csr_outstanding	2.050s	163.472us	20	20	100.00
V2		TOTAL			699	700	99.86
V2S	tl_intg_err	lc_ctrl_sec_cm	36.680s	2.876ms	5	5	100.00
		lc_ctrl_tl_intg_err	4.230s	721.573us	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	4.230s	721.573us	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	22.840s	613.341us	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	35.870s	3.457ms	50	50	100.00
		lc_ctrl_sec_cm	36.680s	2.876ms	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	35.870s	3.457ms	50	50	100.00
		lc_ctrl_sec_cm	36.680s	2.876ms	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	35.870s	3.457ms	50	50	100.00
		lc_ctrl_sec_cm	36.680s	2.876ms	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	35.870s	3.457ms	50	50	100.00
		lc_ctrl_sec_cm	36.680s	2.876ms	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	35.870s	3.457ms	50	50	100.00
		lc_ctrl_sec_cm	36.680s	2.876ms	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	35.870s	3.457ms	50	50	100.00
		lc_ctrl_sec_cm	36.680s	2.876ms	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	35.870s	3.457ms	50	50	100.00
		lc_ctrl_sec_cm	36.680s	2.876ms	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	35.870s	3.457ms	50	50	100.00
		lc_ctrl_sec_cm	36.680s	2.876ms	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	16.530s	709.825us	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	11.630s	128.643us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	32.940s	9.528ms	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	19.070s	8.677ms	39	50	78.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	19.070s	8.677ms	39	50	78.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	21.820s	4.006ms	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	18.380s	582.129us	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	18.380s	582.129us	50	50	100.00
V2S		TOTAL			164	175	93.71
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	34.341m	46.102ms	21	50	42.00
V3		TOTAL			21	50	42.00
		TOTAL			989	1030	96.02

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	26	96.30
V2S	5	5	4	80.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.22	97.92	95.93	93.38	100.00	98.52	98.51	96.29

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:825) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 24 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 24 failures.

    • 0.lc_ctrl_stress_all_with_rand_reset.25674575213362203446516629536422504644472172854348729392272182479864007081853
      Line 40596, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/0.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 29319965605 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 29319965605 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 1.lc_ctrl_stress_all_with_rand_reset.82816335281643419588569310372833763498147035568638713530401247079962185000853
      Line 17982, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/1.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 31762580311 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 31762580311 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 22 more failures.

• UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_sec_mubi_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (* [*] vs * [*]) has 11 failures:

  • Test lc_ctrl_sec_mubi has 11 failures.

    • 1.lc_ctrl_sec_mubi.31544242337998464235071572234736205344824090089490797057274373690342887856510
      Line 600, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/1.lc_ctrl_sec_mubi/latest/run.log

        UVM_ERROR @ 175726524 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_sec_mubi_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 175726524 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 16.lc_ctrl_sec_mubi.71108410385252132807055901697184551218770010969956775245486341125070723232843
      Line 914, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/16.lc_ctrl_sec_mubi/latest/run.log

        UVM_ERROR @  79495795 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_sec_mubi_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
        UVM_INFO @  79495795 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 9 more failures.

• UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (* [*] vs * [*]) has 3 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 2 failures.

    • 2.lc_ctrl_stress_all_with_rand_reset.48270251366391212945986656958735091654346179144481809809388383297426873062751
      Line 16733, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/2.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 35802460629 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 35802460629 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 38.lc_ctrl_stress_all_with_rand_reset.18796949885722489921050787785002007457427330376983349203017651777496025788149
      Line 13216, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/38.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 10193082559 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 10193082559 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test lc_ctrl_errors has 1 failures.

    • 44.lc_ctrl_errors.5971599604277271871606684464050746755343759413207953274616271832995926467606
      Line 4283, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/44.lc_ctrl_errors/latest/run.log

        UVM_ERROR @ 549054183 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 549054183 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Error-[CNST-STOF] Constraint solver timeout failure has 2 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 2 failures.

    • 20.lc_ctrl_stress_all_with_rand_reset.43449503454587872912467281864944604865435055819423673796519052376036354109475
      Line 38670, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/20.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        Error-[CNST-STOF] Constraint solver timeout failure
        ../src/lowrisc_dv_sec_cm_0/prim_sparse_fsm_flop_if.sv, 43
          Exceeded cpu time limit during solve.
          Please use the run-time switch +ntb_solver_cpu_limit to increase the cpu
          limit.  The default cpu limit is 1000 seconds per partition.
      

    • 46.lc_ctrl_stress_all_with_rand_reset.15435590676120631350778656927819345569987339431992382994888209808272562296731
      Line 34953, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/46.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        Error-[CNST-STOF] Constraint solver timeout failure
        ../src/lowrisc_dv_sec_cm_0/prim_sparse_fsm_flop_if.sv, 43
          Exceeded cpu time limit during solve.
          Please use the run-time switch +ntb_solver_cpu_limit to increase the cpu
          limit.  The default cpu limit is 1000 seconds per partition.
      

• UVM_ERROR (cip_base_scoreboard.sv:301) scoreboard [scoreboard] alert fatal_prog_error did not trigger max_delay:* has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 42.lc_ctrl_stress_all_with_rand_reset.12883628231422806356430773550725722636119375761863947145067581697425374363622
      Line 32989, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/42.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 74971130952 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 74971130952 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

• Latest
• 2024.07.02_10.45.34
• 2024.07.02_04.15.00
• 2024.07.01_10.59.33
• 2024.06.30_11.13.55
• 2024.06.29_09.37.35
• 2024.06.28_11.54.21
• 2024.06.27_11.11.42