LC_CTRL/VOLATILE_UNLOCK_DISABLED Simulation Results

Wednesday July 03 2024 23:02:32 UTC

GitHub Revision: e6706fcc7b

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 8083624550445280117614176890238357255195852125596561370221115831648066795492

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	11.010s	198.725us	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.150s	22.988us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.140s	16.998us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	2.870s	508.602us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	1.110s	96.056us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	2.120s	56.121us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.140s	16.998us	20	20	100.00
		lc_ctrl_csr_aliasing	1.110s	96.056us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	10.460s	126.998us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	18.580s	1.102ms	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	0.940s	18.473us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	7.090s	362.078us	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	37.390s	1.296ms	50	50	100.00
V2	lc_errors	lc_ctrl_errors	21.180s	993.263us	50	50	100.00
V2	security_escalation	lc_ctrl_state_failure	37.390s	1.296ms	50	50	100.00
		lc_ctrl_prog_failure	7.090s	362.078us	50	50	100.00
		lc_ctrl_errors	21.180s	993.263us	50	50	100.00
		lc_ctrl_security_escalation	13.960s	1.468ms	50	50	100.00
		lc_ctrl_jtag_state_failure	1.709m	13.009ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	14.920s	973.288us	20	20	100.00
		lc_ctrl_jtag_errors	1.331m	8.422ms	20	20	100.00
V2	jtag_access	lc_ctrl_jtag_smoke	16.860s	9.376ms	20	20	100.00
		lc_ctrl_jtag_state_post_trans	34.040s	8.844ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	14.920s	973.288us	20	20	100.00
		lc_ctrl_jtag_errors	1.331m	8.422ms	20	20	100.00
		lc_ctrl_jtag_access	18.660s	10.344ms	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	36.250s	1.280ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	3.000s	502.177us	10	10	100.00
		lc_ctrl_jtag_csr_rw	2.880s	93.967us	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	49.180s	9.135ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	8.190s	1.019ms	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	2.040s	40.821us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	6.230s	2.158ms	10	10	100.00
		lc_ctrl_jtag_alert_test	4.060s	143.933us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	12.390s	1.218ms	10	10	100.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.380s	35.433us	50	50	100.00
V2	stress_all	lc_ctrl_stress_all	10.933m	40.673ms	49	50	98.00
V2	alert_test	lc_ctrl_alert_test	1.260s	230.952us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	5.590s	154.885us	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	5.590s	154.885us	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.150s	22.988us	5	5	100.00
		lc_ctrl_csr_rw	1.140s	16.998us	20	20	100.00
		lc_ctrl_csr_aliasing	1.110s	96.056us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.990s	102.183us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.150s	22.988us	5	5	100.00
		lc_ctrl_csr_rw	1.140s	16.998us	20	20	100.00
		lc_ctrl_csr_aliasing	1.110s	96.056us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.990s	102.183us	20	20	100.00
V2		TOTAL			699	700	99.86
V2S	tl_intg_err	lc_ctrl_sec_cm	41.790s	229.324us	5	5	100.00
		lc_ctrl_tl_intg_err	4.390s	153.782us	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	4.390s	153.782us	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	18.580s	1.102ms	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	37.390s	1.296ms	50	50	100.00
		lc_ctrl_sec_cm	41.790s	229.324us	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	37.390s	1.296ms	50	50	100.00
		lc_ctrl_sec_cm	41.790s	229.324us	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	37.390s	1.296ms	50	50	100.00
		lc_ctrl_sec_cm	41.790s	229.324us	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	37.390s	1.296ms	50	50	100.00
		lc_ctrl_sec_cm	41.790s	229.324us	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	37.390s	1.296ms	50	50	100.00
		lc_ctrl_sec_cm	41.790s	229.324us	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	37.390s	1.296ms	50	50	100.00
		lc_ctrl_sec_cm	41.790s	229.324us	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	37.390s	1.296ms	50	50	100.00
		lc_ctrl_sec_cm	41.790s	229.324us	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	37.390s	1.296ms	50	50	100.00
		lc_ctrl_sec_cm	41.790s	229.324us	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	13.960s	1.468ms	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	10.460s	126.998us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	34.040s	8.844ms	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	24.320s	644.825us	41	50	82.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	24.320s	644.825us	41	50	82.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	23.270s	1.439ms	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	16.710s	2.298ms	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	16.710s	2.298ms	50	50	100.00
V2S		TOTAL			166	175	94.86
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	2.978h	133.296ms	23	50	46.00
V3		TOTAL			23	50	46.00
		TOTAL			993	1030	96.41

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	26	96.30
V2S	5	5	4	80.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.28	97.92	95.84	93.38	100.00	98.52	99.00	96.29

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:825) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 26 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 26 failures.

    • 1.lc_ctrl_stress_all_with_rand_reset.105451767526921580840042435791122555745804549795443558142525421603516619127224
      Line 11358, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/1.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 96146513483 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 96146513483 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 2.lc_ctrl_stress_all_with_rand_reset.81479933450827872964192641749329303010142304912009825542265184702518081243211
      Line 35000, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/2.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 68478119674 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 68478119674 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 24 more failures.

• UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_sec_mubi_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (* [*] vs * [*]) has 9 failures:

  • Test lc_ctrl_sec_mubi has 9 failures.

    • 2.lc_ctrl_sec_mubi.115003819018369603852277993763880270041394802885246434788414526043302011245636
      Line 1726, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/2.lc_ctrl_sec_mubi/latest/run.log

        UVM_ERROR @ 282948840 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_sec_mubi_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 282948840 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 7.lc_ctrl_sec_mubi.106417526614841189916758221992330457517791503642986881020904821574265760057255
      Line 828, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/7.lc_ctrl_sec_mubi/latest/run.log

        UVM_ERROR @  60202253 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_sec_mubi_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
        UVM_INFO @  60202253 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 7 more failures.

• UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (* [*] vs * [*]) has 1 failures:

  • Test lc_ctrl_stress_all has 1 failures.

    • 28.lc_ctrl_stress_all.78920975853608012052118932417531939406565753193109226485287562998231974476095
      Line 3518, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/28.lc_ctrl_stress_all/latest/run.log

        UVM_ERROR @ 8993334605 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 8993334605 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:551) [lc_ctrl_common_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_state_error fired unexpectedly! has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 31.lc_ctrl_stress_all_with_rand_reset.50096604491085442221504826747238565128450609727585335586555518426586709245659
      Line 28389, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/31.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 62124376998 ps: (cip_base_vseq.sv:551) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
        UVM_INFO @ 62124376998 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

• Latest
• 2024.07.03_01.50.05
• 2024.07.02_10.45.34
• 2024.07.02_04.15.00
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