LC_CTRL/VOLATILE_UNLOCK_DISABLED Simulation Results

Thursday July 04 2024 23:02:28 UTC

GitHub Revision: 3e678c112b

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 94940390549829454688103081328166376218078465228811124044523808815554354133843

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	8.890s	297.281us	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.120s	69.271us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.200s	18.357us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	2.060s	97.390us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	1.770s	592.067us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	1.820s	33.413us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.200s	18.357us	20	20	100.00
		lc_ctrl_csr_aliasing	1.770s	592.067us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	12.160s	116.132us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	26.840s	1.490ms	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	1.020s	14.019us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	5.700s	130.900us	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	41.350s	371.277us	50	50	100.00
V2	lc_errors	lc_ctrl_errors	19.250s	1.899ms	50	50	100.00
V2	security_escalation	lc_ctrl_state_failure	41.350s	371.277us	50	50	100.00
		lc_ctrl_prog_failure	5.700s	130.900us	50	50	100.00
		lc_ctrl_errors	19.250s	1.899ms	50	50	100.00
		lc_ctrl_security_escalation	19.890s	5.979ms	50	50	100.00
		lc_ctrl_jtag_state_failure	2.521m	34.308ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	22.520s	770.110us	20	20	100.00
		lc_ctrl_jtag_errors	2.069m	17.248ms	20	20	100.00
V2	jtag_access	lc_ctrl_jtag_smoke	11.680s	471.003us	20	20	100.00
		lc_ctrl_jtag_state_post_trans	30.270s	963.830us	20	20	100.00
		lc_ctrl_jtag_prog_failure	22.520s	770.110us	20	20	100.00
		lc_ctrl_jtag_errors	2.069m	17.248ms	20	20	100.00
		lc_ctrl_jtag_access	23.100s	1.023ms	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	36.060s	5.173ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	6.780s	281.110us	10	10	100.00
		lc_ctrl_jtag_csr_rw	3.950s	148.456us	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	52.760s	2.470ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	24.070s	5.947ms	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	2.080s	187.274us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	7.690s	301.879us	10	10	100.00
		lc_ctrl_jtag_alert_test	2.290s	410.941us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	20.150s	2.156ms	10	10	100.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.280s	41.369us	50	50	100.00
V2	stress_all	lc_ctrl_stress_all	11.112m	213.094ms	49	50	98.00
V2	alert_test	lc_ctrl_alert_test	1.510s	33.383us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	5.670s	533.979us	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	5.670s	533.979us	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.120s	69.271us	5	5	100.00
		lc_ctrl_csr_rw	1.200s	18.357us	20	20	100.00
		lc_ctrl_csr_aliasing	1.770s	592.067us	5	5	100.00
		lc_ctrl_same_csr_outstanding	2.100s	91.606us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.120s	69.271us	5	5	100.00
		lc_ctrl_csr_rw	1.200s	18.357us	20	20	100.00
		lc_ctrl_csr_aliasing	1.770s	592.067us	5	5	100.00
		lc_ctrl_same_csr_outstanding	2.100s	91.606us	20	20	100.00
V2		TOTAL			699	700	99.86
V2S	tl_intg_err	lc_ctrl_sec_cm	39.580s	840.697us	5	5	100.00
		lc_ctrl_tl_intg_err	4.450s	581.338us	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	4.450s	581.338us	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	26.840s	1.490ms	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	41.350s	371.277us	50	50	100.00
		lc_ctrl_sec_cm	39.580s	840.697us	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	41.350s	371.277us	50	50	100.00
		lc_ctrl_sec_cm	39.580s	840.697us	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	41.350s	371.277us	50	50	100.00
		lc_ctrl_sec_cm	39.580s	840.697us	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	41.350s	371.277us	50	50	100.00
		lc_ctrl_sec_cm	39.580s	840.697us	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	41.350s	371.277us	50	50	100.00
		lc_ctrl_sec_cm	39.580s	840.697us	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	41.350s	371.277us	50	50	100.00
		lc_ctrl_sec_cm	39.580s	840.697us	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	41.350s	371.277us	50	50	100.00
		lc_ctrl_sec_cm	39.580s	840.697us	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	41.350s	371.277us	50	50	100.00
		lc_ctrl_sec_cm	39.580s	840.697us	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	19.890s	5.979ms	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	12.160s	116.132us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	30.270s	963.830us	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	21.780s	3.130ms	46	50	92.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	21.780s	3.130ms	46	50	92.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	24.700s	631.193us	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	19.330s	540.120us	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	19.330s	540.120us	50	50	100.00
V2S		TOTAL			171	175	97.71
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	2.104h	128.620ms	17	50	34.00
V3		TOTAL			17	50	34.00
		TOTAL			992	1030	96.31

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	26	96.30
V2S	5	5	4	80.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.19	97.92	95.66	93.38	100.00	98.52	98.76	96.11

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:825) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 26 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 26 failures.

    • 1.lc_ctrl_stress_all_with_rand_reset.96516343254164588479336998429972024460998046400340618303013697726331290166127
      Line 423, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/1.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 132640507 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 132640507 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 3.lc_ctrl_stress_all_with_rand_reset.83980989534537736015228296920210917790000387996503443016749415370282021697250
      Line 17679, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/3.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 27680833989 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 27680833989 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 24 more failures.

• UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_sec_mubi_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (* [*] vs * [*]) has 4 failures:

  • Test lc_ctrl_sec_mubi has 4 failures.

    • 10.lc_ctrl_sec_mubi.43107402909511320342195719558007043654052154975096046677776874001139963744476
      Line 638, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/10.lc_ctrl_sec_mubi/latest/run.log

        UVM_ERROR @ 102453135 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_sec_mubi_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 102453135 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 17.lc_ctrl_sec_mubi.6513479810022989099692697529624100156367257976153564047979249416550043580996
      Line 456, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/17.lc_ctrl_sec_mubi/latest/run.log

        UVM_ERROR @  23342289 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_sec_mubi_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
        UVM_INFO @  23342289 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 2 more failures.

• Error-[CNST-STOF] Constraint solver timeout failure has 2 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 2 failures.

    • 5.lc_ctrl_stress_all_with_rand_reset.109114679220529258801590049603895447552273529409370963586738286377729202056016
      Line 38681, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/5.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        Error-[CNST-STOF] Constraint solver timeout failure
        ../src/lowrisc_dv_sec_cm_0/prim_sparse_fsm_flop_if.sv, 43
          Exceeded cpu time limit during solve.
          Please use the run-time switch +ntb_solver_cpu_limit to increase the cpu
          limit.  The default cpu limit is 1000 seconds per partition.
      

    • 22.lc_ctrl_stress_all_with_rand_reset.50852443583200038234990482946355966481458828903757788243626714611139869419017
      Line 43813, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/22.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        Error-[CNST-STOF] Constraint solver timeout failure
        ../src/lowrisc_dv_sec_cm_0/prim_sparse_fsm_flop_if.sv, 43
          Exceeded cpu time limit during solve.
          Please use the run-time switch +ntb_solver_cpu_limit to increase the cpu
          limit.  The default cpu limit is 1000 seconds per partition.
      

• UVM_ERROR (cip_base_scoreboard.sv:301) scoreboard [scoreboard] alert fatal_prog_error did not trigger max_delay:* has 2 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 2 failures.

    • 18.lc_ctrl_stress_all_with_rand_reset.8462453750747601418517588173183671144699183485057819440424537995485619680458
      Line 19606, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/18.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 60860237404 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 60860237404 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 47.lc_ctrl_stress_all_with_rand_reset.86445690405997991878443699390248019775010672385725037582877215331397602911709
      Line 13083, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/47.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 23681489856 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 23681489856 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:551) [lc_ctrl_common_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_state_error fired unexpectedly! has 2 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 2 failures.

    • 43.lc_ctrl_stress_all_with_rand_reset.107256404760605600446074249765653763848190694247525933174737737912143531328058
      Line 29119, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/43.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 25118219058 ps: (cip_base_vseq.sv:551) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
        UVM_INFO @ 25118219058 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 49.lc_ctrl_stress_all_with_rand_reset.81360987029204671224353552533589899639226558355841105042531509502017870180291
      Line 44749, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/49.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 120314205925 ps: (cip_base_vseq.sv:551) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
        UVM_INFO @ 120314205925 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:749) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 21.lc_ctrl_stress_all_with_rand_reset.48709307387641632817716051685422587881689257775100824077044400747259412126217
      Line 547, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/21.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @  47578894 ps: (cip_base_vseq.sv:749) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
        UVM_INFO @  47578894 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (* [*] vs * [*]) has 1 failures:

  • Test lc_ctrl_stress_all has 1 failures.

    • 23.lc_ctrl_stress_all.85678546928626039236987002001957488913742985404311933486754915211500767357369
      Line 2585, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/23.lc_ctrl_stress_all/latest/run.log

        UVM_ERROR @ 1073110959 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 1073110959 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

• Latest
• 2024.07.04_11.16.29
• 2024.07.03_01.50.05
• 2024.07.02_10.45.34
• 2024.07.02_04.15.00
• 2024.07.01_10.59.33
• 2024.06.30_11.13.55
• 2024.06.29_09.37.35