LC_CTRL/VOLATILE_UNLOCK_DISABLED Simulation Results

Friday July 05 2024 23:02:55 UTC

GitHub Revision: 9edf84e236

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 47623749544922802985321435118963335754001495105472137721881337469861493653463

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	12.690s	183.432us	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.330s	20.667us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.110s	87.747us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	2.130s	55.666us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	1.640s	102.621us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	2.210s	29.559us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.110s	87.747us	20	20	100.00
		lc_ctrl_csr_aliasing	1.640s	102.621us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	11.230s	90.551us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	25.170s	1.540ms	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	0.980s	21.283us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	6.600s	1.526ms	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	38.260s	276.096us	50	50	100.00
V2	lc_errors	lc_ctrl_errors	20.560s	1.925ms	50	50	100.00
V2	security_escalation	lc_ctrl_state_failure	38.260s	276.096us	50	50	100.00
		lc_ctrl_prog_failure	6.600s	1.526ms	50	50	100.00
		lc_ctrl_errors	20.560s	1.925ms	50	50	100.00
		lc_ctrl_security_escalation	16.120s	675.252us	50	50	100.00
		lc_ctrl_jtag_state_failure	2.186m	6.669ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	21.930s	3.299ms	20	20	100.00
		lc_ctrl_jtag_errors	1.643m	11.870ms	20	20	100.00
V2	jtag_access	lc_ctrl_jtag_smoke	15.520s	2.608ms	20	20	100.00
		lc_ctrl_jtag_state_post_trans	29.230s	879.585us	20	20	100.00
		lc_ctrl_jtag_prog_failure	21.930s	3.299ms	20	20	100.00
		lc_ctrl_jtag_errors	1.643m	11.870ms	20	20	100.00
		lc_ctrl_jtag_access	25.800s	1.120ms	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	21.030s	8.387ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	3.570s	122.686us	10	10	100.00
		lc_ctrl_jtag_csr_rw	4.320s	874.666us	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	44.610s	4.120ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	16.710s	732.312us	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	1.950s	85.445us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	7.870s	1.240ms	10	10	100.00
		lc_ctrl_jtag_alert_test	2.200s	322.390us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	15.520s	10.012ms	9	10	90.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.280s	22.262us	50	50	100.00
V2	stress_all	lc_ctrl_stress_all	8.034m	49.137ms	50	50	100.00
V2	alert_test	lc_ctrl_alert_test	1.430s	28.030us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	4.490s	128.506us	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	4.490s	128.506us	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.330s	20.667us	5	5	100.00
		lc_ctrl_csr_rw	1.110s	87.747us	20	20	100.00
		lc_ctrl_csr_aliasing	1.640s	102.621us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.840s	565.257us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.330s	20.667us	5	5	100.00
		lc_ctrl_csr_rw	1.110s	87.747us	20	20	100.00
		lc_ctrl_csr_aliasing	1.640s	102.621us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.840s	565.257us	20	20	100.00
V2		TOTAL			699	700	99.86
V2S	tl_intg_err	lc_ctrl_sec_cm	42.920s	878.273us	5	5	100.00
		lc_ctrl_tl_intg_err	3.770s	159.511us	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	3.770s	159.511us	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	25.170s	1.540ms	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	38.260s	276.096us	50	50	100.00
		lc_ctrl_sec_cm	42.920s	878.273us	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	38.260s	276.096us	50	50	100.00
		lc_ctrl_sec_cm	42.920s	878.273us	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	38.260s	276.096us	50	50	100.00
		lc_ctrl_sec_cm	42.920s	878.273us	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	38.260s	276.096us	50	50	100.00
		lc_ctrl_sec_cm	42.920s	878.273us	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	38.260s	276.096us	50	50	100.00
		lc_ctrl_sec_cm	42.920s	878.273us	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	38.260s	276.096us	50	50	100.00
		lc_ctrl_sec_cm	42.920s	878.273us	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	38.260s	276.096us	50	50	100.00
		lc_ctrl_sec_cm	42.920s	878.273us	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	38.260s	276.096us	50	50	100.00
		lc_ctrl_sec_cm	42.920s	878.273us	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	16.120s	675.252us	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	11.230s	90.551us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	29.230s	879.585us	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	21.070s	3.076ms	39	50	78.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	21.070s	3.076ms	39	50	78.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	26.350s	1.150ms	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	17.240s	5.138ms	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	17.240s	5.138ms	50	50	100.00
V2S		TOTAL			164	175	93.71
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	26.991m	16.749ms	23	50	46.00
V3		TOTAL			23	50	46.00
		TOTAL			991	1030	96.21

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	26	96.30
V2S	5	5	4	80.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.84	97.92	95.84	93.38	97.62	98.52	98.51	96.11

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:825) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 22 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 22 failures.

    • 1.lc_ctrl_stress_all_with_rand_reset.112740847977734153275690450258541428059508910908277867357829903545717995036536
      Line 38578, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/1.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 93639435521 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 93639435521 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 3.lc_ctrl_stress_all_with_rand_reset.40191312141062675431656925805746176705776660438390798510040575734665562690364
      Line 21453, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/3.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 183144323036 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 183144323036 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 20 more failures.

• UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_sec_mubi_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (* [*] vs * [*]) has 11 failures:

  • Test lc_ctrl_sec_mubi has 11 failures.

    • 3.lc_ctrl_sec_mubi.26860017137437140666585171999762960639988995133200041137276456433330077045774
      Line 786, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/3.lc_ctrl_sec_mubi/latest/run.log

        UVM_ERROR @  36723278 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_sec_mubi_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
        UVM_INFO @  36723278 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 4.lc_ctrl_sec_mubi.67976941998339349077945534807902154887319122261432730883137056168317828052620
      Line 3098, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/4.lc_ctrl_sec_mubi/latest/run.log

        UVM_ERROR @ 245699910 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_sec_mubi_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 245699910 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 9 more failures.

• Error-[CNST-STOF] Constraint solver timeout failure has 2 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 2 failures.

    • 28.lc_ctrl_stress_all_with_rand_reset.75280808087932940236625216332521981333514148806068307032138704591816890221800
      Line 28752, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/28.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        Error-[CNST-STOF] Constraint solver timeout failure
        ../src/lowrisc_dv_sec_cm_0/prim_sparse_fsm_flop_if.sv, 43
          Exceeded cpu time limit during solve.
          Please use the run-time switch +ntb_solver_cpu_limit to increase the cpu
          limit.  The default cpu limit is 1000 seconds per partition.
      

    • 29.lc_ctrl_stress_all_with_rand_reset.112890352632840009821185605496568940489463583571510994606688939844802791773427
      Line 39139, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/29.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        Error-[CNST-STOF] Constraint solver timeout failure
        ../src/lowrisc_dv_sec_cm_0/prim_sparse_fsm_flop_if.sv, 43
          Exceeded cpu time limit during solve.
          Please use the run-time switch +ntb_solver_cpu_limit to increase the cpu
          limit.  The default cpu limit is 1000 seconds per partition.
      

• UVM_FATAL (lc_ctrl_jtag_priority_vseq.sv:113) [lc_ctrl_jtag_priority_vseq] timeout occurred! has 1 failures:

  • Test lc_ctrl_jtag_priority has 1 failures.

    • 3.lc_ctrl_jtag_priority.12830249130460113558219641191194715174041244326415653360768796618977127100525
      Line 461, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/3.lc_ctrl_jtag_priority/latest/run.log

        UVM_FATAL @ 10012020153 ps: (lc_ctrl_jtag_priority_vseq.sv:113) [uvm_test_top.env.virtual_sequencer.lc_ctrl_jtag_priority_vseq] timeout occurred!
        UVM_INFO @ 10012020153 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Job lc_ctrl_volatile_unlock_disabled-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 9.lc_ctrl_stress_all_with_rand_reset.59027956120637001784449633600310807478503735252045860343038711555755875696144
      Log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/9.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        Job ID: smart:a2431149-a540-439b-852d-afdf350e5130
      

• UVM_ERROR (cip_base_vseq.sv:551) [lc_ctrl_common_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_state_error fired unexpectedly! has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 31.lc_ctrl_stress_all_with_rand_reset.47599142398825713546049084185244674978832687152306416590066193471612481328056
      Line 19157, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/31.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 17944551139 ps: (cip_base_vseq.sv:551) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
        UVM_INFO @ 17944551139 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (* [*] vs * [*]) has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 41.lc_ctrl_stress_all_with_rand_reset.85473161249652844152182616029333586377113533264756171710141395332208788664394
      Line 21736, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/41.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 43520028641 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 43520028641 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

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