LC_CTRL/VOLATILE_UNLOCK_DISABLED Simulation Results

Saturday July 06 2024 23:02:28 UTC

GitHub Revision: `c42c47ec2d`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 3200059823452722292543998130245428086525417237473114929151723951411399280153

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	10.270s	361.374us	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.150s	12.944us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.140s	31.523us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	1.950s	39.390us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	1.620s	161.353us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	2.120s	28.384us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.140s	31.523us	20	20	100.00
		lc_ctrl_csr_aliasing	1.620s	161.353us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	9.550s	44.930us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	23.670s	994.891us	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	0.970s	21.892us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	5.040s	113.976us	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	34.490s	323.059us	50	50	100.00
V2	lc_errors	lc_ctrl_errors	22.870s	1.098ms	48	50	96.00
V2	security_escalation	lc_ctrl_state_failure	34.490s	323.059us	50	50	100.00
		lc_ctrl_prog_failure	5.040s	113.976us	50	50	100.00
		lc_ctrl_errors	22.870s	1.098ms	48	50	96.00
		lc_ctrl_security_escalation	17.520s	932.891us	50	50	100.00
		lc_ctrl_jtag_state_failure	1.702m	13.975ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	18.140s	12.920ms	20	20	100.00
		lc_ctrl_jtag_errors	2.279m	5.241ms	20	20	100.00
V2	jtag_access	lc_ctrl_jtag_smoke	12.830s	1.966ms	20	20	100.00
		lc_ctrl_jtag_state_post_trans	25.650s	1.224ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	18.140s	12.920ms	20	20	100.00
		lc_ctrl_jtag_errors	2.279m	5.241ms	20	20	100.00
		lc_ctrl_jtag_access	29.060s	1.260ms	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	36.450s	2.125ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	3.110s	197.949us	10	10	100.00
		lc_ctrl_jtag_csr_rw	2.270s	63.889us	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	21.850s	3.324ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	25.260s	1.161ms	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	1.980s	177.550us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	6.340s	431.675us	10	10	100.00
		lc_ctrl_jtag_alert_test	3.100s	115.261us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	16.370s	1.644ms	10	10	100.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.150s	13.992us	50	50	100.00
V2	stress_all	lc_ctrl_stress_all	15.367m	28.513ms	50	50	100.00
V2	alert_test	lc_ctrl_alert_test	1.330s	122.632us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	3.920s	173.383us	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	3.920s	173.383us	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.150s	12.944us	5	5	100.00
		lc_ctrl_csr_rw	1.140s	31.523us	20	20	100.00
		lc_ctrl_csr_aliasing	1.620s	161.353us	5	5	100.00
		lc_ctrl_same_csr_outstanding	2.020s	46.839us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.150s	12.944us	5	5	100.00
		lc_ctrl_csr_rw	1.140s	31.523us	20	20	100.00
		lc_ctrl_csr_aliasing	1.620s	161.353us	5	5	100.00
		lc_ctrl_same_csr_outstanding	2.020s	46.839us	20	20	100.00
V2		TOTAL			698	700	99.71
V2S	tl_intg_err	lc_ctrl_sec_cm	36.590s	612.655us	5	5	100.00
		lc_ctrl_tl_intg_err	4.070s	353.038us	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	4.070s	353.038us	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	23.670s	994.891us	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	34.490s	323.059us	50	50	100.00
		lc_ctrl_sec_cm	36.590s	612.655us	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	34.490s	323.059us	50	50	100.00
		lc_ctrl_sec_cm	36.590s	612.655us	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	34.490s	323.059us	50	50	100.00
		lc_ctrl_sec_cm	36.590s	612.655us	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	34.490s	323.059us	50	50	100.00
		lc_ctrl_sec_cm	36.590s	612.655us	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	34.490s	323.059us	50	50	100.00
		lc_ctrl_sec_cm	36.590s	612.655us	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	34.490s	323.059us	50	50	100.00
		lc_ctrl_sec_cm	36.590s	612.655us	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	34.490s	323.059us	50	50	100.00
		lc_ctrl_sec_cm	36.590s	612.655us	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	34.490s	323.059us	50	50	100.00
		lc_ctrl_sec_cm	36.590s	612.655us	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	17.520s	932.891us	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	9.550s	44.930us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	25.650s	1.224ms	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	19.450s	2.010ms	40	50	80.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	19.450s	2.010ms	40	50	80.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	27.800s	3.947ms	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	22.280s	747.441us	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	22.280s	747.441us	50	50	100.00
V2S		TOTAL			165	175	94.29
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	35.978m	85.687ms	19	50	38.00
V3		TOTAL			19	50	38.00
		TOTAL			987	1030	95.83

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	26	96.30
V2S	5	5	4	80.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.23	97.92	95.56	93.38	100.00	98.52	98.76	96.47

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:825) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 24 failures:
- Test lc_ctrl_stress_all_with_rand_reset has 24 failures.
  - 1.lc_ctrl_stress_all_with_rand_reset.57428600614217680025770357187722766326487280780734325684681211655412057038290
    Line 1664, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/1.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 3766599487 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 3766599487 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 5.lc_ctrl_stress_all_with_rand_reset.68380528442577309187938384185943660605053896644328194873592445360636522186736
    Line 9935, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/5.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 9743647037 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10003 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 9743647037 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 22 more failures.
UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_sec_mubi_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (* [*] vs * [*]) has 10 failures:
- Test lc_ctrl_sec_mubi has 10 failures.
  - 3.lc_ctrl_sec_mubi.1233851271756485844113441641664264057955143491342569828904157785715230278019
    Line 954, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/3.lc_ctrl_sec_mubi/latest/run.log
```
  UVM_ERROR @ 188857703 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_sec_mubi_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 188857703 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 10.lc_ctrl_sec_mubi.95903095149771901599763223260991331787186181769867930695809941003177522246139
    Line 3570, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/10.lc_ctrl_sec_mubi/latest/run.log
```
  UVM_ERROR @ 523803505 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_sec_mubi_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 523803505 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 8 more failures.
UVM_ERROR (cip_base_vseq.sv:551) [lc_ctrl_common_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_state_error fired unexpectedly! has 5 failures:
- Test lc_ctrl_stress_all_with_rand_reset has 5 failures.
  - 6.lc_ctrl_stress_all_with_rand_reset.10329014156819080117780346456057854980274787410779327225872163628088650753630
    Line 51100, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/6.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 51688086345 ps: (cip_base_vseq.sv:551) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
  UVM_INFO @ 51688086345 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 8.lc_ctrl_stress_all_with_rand_reset.1696326130388090506668348662154347321698844229768511759106423853420870798753
    Line 19764, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/8.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 8999780977 ps: (cip_base_vseq.sv:551) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
  UVM_INFO @ 8999780977 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 3 more failures.
UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (* [*] vs * [*]) has 1 failures:
- Test lc_ctrl_errors has 1 failures.
  - 21.lc_ctrl_errors.791276629618498008997142943102739629741532623825784916448638667839243835415
    Line 1081, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/21.lc_ctrl_errors/latest/run.log
```
  UVM_ERROR @  72550869 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
  UVM_INFO @  72550869 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:551) [lc_ctrl_smoke_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_prog_error fired unexpectedly! has 1 failures:
- Test lc_ctrl_stress_all_with_rand_reset has 1 failures.
  - 22.lc_ctrl_stress_all_with_rand_reset.63523562054033231805088729754279164398460272907683633259687424713835301640985
    Line 6725, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/22.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 905000476 ps: (cip_base_vseq.sv:551) [uvm_test_top.env.virtual_sequencer.lc_ctrl_smoke_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_prog_error fired unexpectedly!
  UVM_INFO @ 905000476 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (lc_ctrl_errors_vseq.sv:769) [lc_ctrl_lc_errors_vseq] Check failed otp_error_act == otp_error_exp (* [*] vs * [*]) has 1 failures:
- Test lc_ctrl_errors has 1 failures.
  - 36.lc_ctrl_errors.47961692199323805615546538450713152715049043525620140163897152945174884785840
    Line 1256, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/36.lc_ctrl_errors/latest/run.log
```
  UVM_ERROR @ 507373564 ps: (lc_ctrl_errors_vseq.sv:769) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed otp_error_act == otp_error_exp (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 507373564 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_scoreboard.sv:301) scoreboard [scoreboard] alert fatal_prog_error did not trigger max_delay:* has 1 failures:
- Test lc_ctrl_stress_all_with_rand_reset has 1 failures.
  - 40.lc_ctrl_stress_all_with_rand_reset.102146150096862002472084084749460059144009645120225192036560113114188715651954
    Line 13209, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/40.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 16525845583 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
  UVM_INFO @ 16525845583 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

LC_CTRL/VOLATILE_UNLOCK_DISABLED Simulation Results

Saturday July 06 2024 23:02:28 UTC

GitHub Revision: c42c47ec2d

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 3200059823452722292543998130245428086525417237473114929151723951411399280153

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `c42c47ec2d`