LC_CTRL/VOLATILE_UNLOCK_DISABLED Simulation Results

Sunday July 07 2024 23:02:38 UTC

GitHub Revision: 2e5d86c9b5

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 75221189197949424635294305394615322888112457483844341597147780944629972574676

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	7.220s	781.631us	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.060s	21.968us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.100s	22.373us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	2.600s	257.430us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	1.860s	40.854us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	2.350s	28.861us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.100s	22.373us	20	20	100.00
		lc_ctrl_csr_aliasing	1.860s	40.854us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	9.090s	123.844us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	22.390s	382.782us	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	0.980s	11.748us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	5.520s	257.915us	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	36.690s	1.284ms	50	50	100.00
V2	lc_errors	lc_ctrl_errors	27.680s	1.444ms	50	50	100.00
V2	security_escalation	lc_ctrl_state_failure	36.690s	1.284ms	50	50	100.00
		lc_ctrl_prog_failure	5.520s	257.915us	50	50	100.00
		lc_ctrl_errors	27.680s	1.444ms	50	50	100.00
		lc_ctrl_security_escalation	14.750s	356.469us	50	50	100.00
		lc_ctrl_jtag_state_failure	1.584m	5.441ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	26.720s	3.663ms	20	20	100.00
		lc_ctrl_jtag_errors	1.640m	48.291ms	20	20	100.00
V2	jtag_access	lc_ctrl_jtag_smoke	11.490s	3.723ms	20	20	100.00
		lc_ctrl_jtag_state_post_trans	23.850s	1.289ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	26.720s	3.663ms	20	20	100.00
		lc_ctrl_jtag_errors	1.640m	48.291ms	20	20	100.00
		lc_ctrl_jtag_access	19.660s	803.533us	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	32.230s	1.089ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	4.950s	785.542us	10	10	100.00
		lc_ctrl_jtag_csr_rw	4.170s	164.176us	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	34.400s	4.421ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	18.120s	3.057ms	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	1.370s	274.111us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	5.950s	516.426us	10	10	100.00
		lc_ctrl_jtag_alert_test	2.280s	72.662us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	24.420s	2.633ms	10	10	100.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.150s	73.395us	50	50	100.00
V2	stress_all	lc_ctrl_stress_all	15.819m	60.883ms	48	50	96.00
V2	alert_test	lc_ctrl_alert_test	1.490s	49.120us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	4.630s	1.373ms	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	4.630s	1.373ms	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.060s	21.968us	5	5	100.00
		lc_ctrl_csr_rw	1.100s	22.373us	20	20	100.00
		lc_ctrl_csr_aliasing	1.860s	40.854us	5	5	100.00
		lc_ctrl_same_csr_outstanding	2.000s	50.962us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.060s	21.968us	5	5	100.00
		lc_ctrl_csr_rw	1.100s	22.373us	20	20	100.00
		lc_ctrl_csr_aliasing	1.860s	40.854us	5	5	100.00
		lc_ctrl_same_csr_outstanding	2.000s	50.962us	20	20	100.00
V2		TOTAL			698	700	99.71
V2S	tl_intg_err	lc_ctrl_sec_cm	34.130s	1.016ms	5	5	100.00
		lc_ctrl_tl_intg_err	4.110s	118.416us	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	4.110s	118.416us	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	22.390s	382.782us	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	36.690s	1.284ms	50	50	100.00
		lc_ctrl_sec_cm	34.130s	1.016ms	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	36.690s	1.284ms	50	50	100.00
		lc_ctrl_sec_cm	34.130s	1.016ms	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	36.690s	1.284ms	50	50	100.00
		lc_ctrl_sec_cm	34.130s	1.016ms	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	36.690s	1.284ms	50	50	100.00
		lc_ctrl_sec_cm	34.130s	1.016ms	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	36.690s	1.284ms	50	50	100.00
		lc_ctrl_sec_cm	34.130s	1.016ms	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	36.690s	1.284ms	50	50	100.00
		lc_ctrl_sec_cm	34.130s	1.016ms	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	36.690s	1.284ms	50	50	100.00
		lc_ctrl_sec_cm	34.130s	1.016ms	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	36.690s	1.284ms	50	50	100.00
		lc_ctrl_sec_cm	34.130s	1.016ms	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	14.750s	356.469us	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	9.090s	123.844us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	23.850s	1.289ms	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	33.690s	759.078us	39	50	78.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	33.690s	759.078us	39	50	78.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	22.310s	9.660ms	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	15.330s	645.802us	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	15.330s	645.802us	50	50	100.00
V2S		TOTAL			164	175	93.71
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	38.673m	66.038ms	23	50	46.00
V3		TOTAL			23	50	46.00
		TOTAL			990	1030	96.12

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	26	96.30
V2S	5	5	4	80.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.27	97.92	95.93	93.38	100.00	98.52	99.00	96.11

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:825) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 24 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 24 failures.

    • 1.lc_ctrl_stress_all_with_rand_reset.111926888123473972779953006389353191222296158376324804596040227734026929885030
      Line 21890, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/1.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 22597539992 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 22597539992 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 5.lc_ctrl_stress_all_with_rand_reset.15817588112582810116014272100686447473993543713417921587319111038974711605650
      Line 12623, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/5.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 45660172148 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 45660172148 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 22 more failures.

• UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_sec_mubi_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (* [*] vs * [*]) has 11 failures:

  • Test lc_ctrl_sec_mubi has 11 failures.

    • 7.lc_ctrl_sec_mubi.75671900378956646314768052924350489303187925269327723418812925679657699312287
      Line 2170, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/7.lc_ctrl_sec_mubi/latest/run.log

        UVM_ERROR @ 733586157 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_sec_mubi_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 733586157 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 11.lc_ctrl_sec_mubi.97807668372324113732837593020533878984640264580057882147304174611487653135970
      Line 2334, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/11.lc_ctrl_sec_mubi/latest/run.log

        UVM_ERROR @ 592582754 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_sec_mubi_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 592582754 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 9 more failures.

• UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (* [*] vs * [*]) has 3 failures:

  • Test lc_ctrl_stress_all has 2 failures.

    • 3.lc_ctrl_stress_all.7429864054046732368856684515931306668601347606046027936084405923872314444294
      Line 2457, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/3.lc_ctrl_stress_all/latest/run.log

        UVM_ERROR @ 3226939868 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 3226939868 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 39.lc_ctrl_stress_all.21062383755473553652332688496278036959128815630467646783134242858252391799148
      Line 5023, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/39.lc_ctrl_stress_all/latest/run.log

        UVM_ERROR @ 1502814118 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 1502814118 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 22.lc_ctrl_stress_all_with_rand_reset.35343248575730609978481900484945546977598308531925016124675830586163573259214
      Line 4086, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/22.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1091488644 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 1091488644 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:551) [lc_ctrl_common_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_state_error fired unexpectedly! has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 2.lc_ctrl_stress_all_with_rand_reset.93108606250017724813582954301110269474840549190788540228676706478264599880972
      Line 24013, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/2.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 75286243159 ps: (cip_base_vseq.sv:551) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
        UVM_INFO @ 75286243159 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Error-[CNST-STOF] Constraint solver timeout failure has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 41.lc_ctrl_stress_all_with_rand_reset.27266175043963196985465857511695652686267332078657840356730895256425178161895
      Line 38757, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/41.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        Error-[CNST-STOF] Constraint solver timeout failure
        ../src/lowrisc_dv_sec_cm_0/prim_sparse_fsm_flop_if.sv, 43
          Exceeded cpu time limit during solve.
          Please use the run-time switch +ntb_solver_cpu_limit to increase the cpu
          limit.  The default cpu limit is 1000 seconds per partition.
      

Past Results

• Latest
• 2024.07.07_10.35.12
• 2024.07.06_10.42.49
• 2024.07.05_11.07.21
• 2024.07.04_11.16.29
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