LC_CTRL/VOLATILE_UNLOCK_DISABLED Simulation Results

Tuesday July 09 2024 23:02:48 UTC

GitHub Revision: 6a84251492

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 61727890964832844865465694323650730626175387240181955975848876152363892893427

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	10.660s	277.305us	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.120s	34.352us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.060s	24.401us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	2.640s	68.986us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	1.760s	123.658us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	2.130s	52.178us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.060s	24.401us	20	20	100.00
		lc_ctrl_csr_aliasing	1.760s	123.658us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	10.320s	287.666us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	23.360s	2.755ms	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	1.000s	11.579us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	7.000s	724.962us	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	38.440s	1.423ms	50	50	100.00
V2	lc_errors	lc_ctrl_errors	21.830s	1.132ms	49	50	98.00
V2	security_escalation	lc_ctrl_state_failure	38.440s	1.423ms	50	50	100.00
		lc_ctrl_prog_failure	7.000s	724.962us	50	50	100.00
		lc_ctrl_errors	21.830s	1.132ms	49	50	98.00
		lc_ctrl_security_escalation	16.290s	381.004us	50	50	100.00
		lc_ctrl_jtag_state_failure	1.359m	9.625ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	13.630s	447.393us	20	20	100.00
		lc_ctrl_jtag_errors	1.907m	4.205ms	20	20	100.00
V2	jtag_access	lc_ctrl_jtag_smoke	17.510s	2.860ms	20	20	100.00
		lc_ctrl_jtag_state_post_trans	21.990s	3.582ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	13.630s	447.393us	20	20	100.00
		lc_ctrl_jtag_errors	1.907m	4.205ms	20	20	100.00
		lc_ctrl_jtag_access	22.480s	930.272us	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	34.810s	1.311ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	3.370s	107.758us	10	10	100.00
		lc_ctrl_jtag_csr_rw	2.530s	1.069ms	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	50.130s	12.461ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	13.060s	517.192us	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	1.500s	21.014us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	6.390s	1.244ms	10	10	100.00
		lc_ctrl_jtag_alert_test	1.830s	220.746us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	7.700s	2.062ms	10	10	100.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.370s	19.613us	50	50	100.00
V2	stress_all	lc_ctrl_stress_all	8.598m	15.003ms	50	50	100.00
V2	alert_test	lc_ctrl_alert_test	1.380s	25.043us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	4.950s	124.775us	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	4.950s	124.775us	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.120s	34.352us	5	5	100.00
		lc_ctrl_csr_rw	1.060s	24.401us	20	20	100.00
		lc_ctrl_csr_aliasing	1.760s	123.658us	5	5	100.00
		lc_ctrl_same_csr_outstanding	2.110s	45.748us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.120s	34.352us	5	5	100.00
		lc_ctrl_csr_rw	1.060s	24.401us	20	20	100.00
		lc_ctrl_csr_aliasing	1.760s	123.658us	5	5	100.00
		lc_ctrl_same_csr_outstanding	2.110s	45.748us	20	20	100.00
V2		TOTAL			699	700	99.86
V2S	tl_intg_err	lc_ctrl_sec_cm	38.690s	2.731ms	5	5	100.00
		lc_ctrl_tl_intg_err	5.510s	721.168us	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	5.510s	721.168us	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	23.360s	2.755ms	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	38.440s	1.423ms	50	50	100.00
		lc_ctrl_sec_cm	38.690s	2.731ms	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	38.440s	1.423ms	50	50	100.00
		lc_ctrl_sec_cm	38.690s	2.731ms	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	38.440s	1.423ms	50	50	100.00
		lc_ctrl_sec_cm	38.690s	2.731ms	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	38.440s	1.423ms	50	50	100.00
		lc_ctrl_sec_cm	38.690s	2.731ms	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	38.440s	1.423ms	50	50	100.00
		lc_ctrl_sec_cm	38.690s	2.731ms	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	38.440s	1.423ms	50	50	100.00
		lc_ctrl_sec_cm	38.690s	2.731ms	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	38.440s	1.423ms	50	50	100.00
		lc_ctrl_sec_cm	38.690s	2.731ms	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	38.440s	1.423ms	50	50	100.00
		lc_ctrl_sec_cm	38.690s	2.731ms	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	16.290s	381.004us	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	10.320s	287.666us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	21.990s	3.582ms	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	22.480s	6.074ms	42	50	84.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	22.480s	6.074ms	42	50	84.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	23.770s	1.250ms	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	23.320s	764.536us	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	23.320s	764.536us	50	50	100.00
V2S		TOTAL			167	175	95.43
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	36.746m	32.978ms	21	50	42.00
V3		TOTAL			21	50	42.00
		TOTAL			992	1030	96.31

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	26	96.30
V2S	5	5	4	80.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.25	97.92	96.12	93.38	100.00	98.52	98.51	96.29

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:825) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 24 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 24 failures.

    • 0.lc_ctrl_stress_all_with_rand_reset.2408068682847048166325826898173484548575217630747582103159395833340329688586
      Line 8929, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/0.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 22641437048 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10006 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 22641437048 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 1.lc_ctrl_stress_all_with_rand_reset.36699770670938373059904066354026770314580110825878599049421721033936141590008
      Line 15854, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/1.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 21648117706 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 21648117706 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 22 more failures.

• UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_sec_mubi_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (* [*] vs * [*]) has 8 failures:

  • Test lc_ctrl_sec_mubi has 8 failures.

    • 2.lc_ctrl_sec_mubi.115522234201017932334535336235235625643539507048164826961268402318713131838311
      Line 2392, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/2.lc_ctrl_sec_mubi/latest/run.log

        UVM_ERROR @ 182926045 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_sec_mubi_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 182926045 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 3.lc_ctrl_sec_mubi.58032808224459233313086722670320154404649384030041809941789804760800678691181
      Line 1770, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/3.lc_ctrl_sec_mubi/latest/run.log

        UVM_ERROR @ 170291524 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_sec_mubi_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 170291524 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 6 more failures.

• Job lc_ctrl_volatile_unlock_disabled-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 2 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 2 failures.

    • 20.lc_ctrl_stress_all_with_rand_reset.62103493465264617030978745348679466251004248968925457158807792868484926997715
      Log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/20.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        Job ID: smart:99d57b0b-cd7f-475b-9e65-94d97a2a22f6
      

    • 22.lc_ctrl_stress_all_with_rand_reset.45954129207910446705034236775873822478047784474309857565417639436995533058580
      Log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/22.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        Job ID: smart:c72c55b8-e9e8-43c1-bc70-67c15383c8e9
      

• UVM_ERROR (cip_base_scoreboard.sv:301) scoreboard [scoreboard] alert fatal_prog_error did not trigger max_delay:* has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 4.lc_ctrl_stress_all_with_rand_reset.71678854595407859307322206620105613331342929003050866622175057008566498125820
      Line 4649, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/4.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 8356131349 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 8356131349 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Error-[CNST-STOF] Constraint solver timeout failure has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 15.lc_ctrl_stress_all_with_rand_reset.30108480594779914570777344634204807098567548971621879626033934546045684092987
      Line 52254, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/15.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        Error-[CNST-STOF] Constraint solver timeout failure
        ../src/lowrisc_dv_sec_cm_0/prim_sparse_fsm_flop_if.sv, 43
          Exceeded cpu time limit during solve.
          Please use the run-time switch +ntb_solver_cpu_limit to increase the cpu
          limit.  The default cpu limit is 1000 seconds per partition.
      

• UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (* [*] vs * [*]) has 1 failures:

  • Test lc_ctrl_errors has 1 failures.

    • 21.lc_ctrl_errors.89364047431908981462991850167743168802057089095949707128418813756691871214062
      Line 2872, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/21.lc_ctrl_errors/latest/run.log

        UVM_ERROR @ 1850082940 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 1850082940 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:551) [lc_ctrl_common_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_state_error fired unexpectedly! has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 49.lc_ctrl_stress_all_with_rand_reset.88876582561866440971425430032179299480467760224148303440630668263355148945646
      Line 31210, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/49.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 77631560888 ps: (cip_base_vseq.sv:551) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
        UVM_INFO @ 77631560888 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

• Latest
• 2024.07.08_10.12.42
• 2024.07.07_10.35.12
• 2024.07.06_10.42.49
• 2024.07.05_11.07.21
• 2024.07.04_11.16.29
• 2024.07.03_01.50.05
• 2024.07.02_10.45.34