LC_CTRL/VOLATILE_UNLOCK_DISABLED Simulation Results

Wednesday July 10 2024 23:02:26 UTC

GitHub Revision: 39211701b5

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 52262812535389540465251148247405743574935129745685597413714598750252192397067

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	9.910s	286.461us	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.280s	17.705us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.210s	17.121us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	2.710s	65.272us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	1.550s	279.809us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	2.140s	31.421us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.210s	17.121us	20	20	100.00
		lc_ctrl_csr_aliasing	1.550s	279.809us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	10.480s	147.179us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	25.600s	3.165ms	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	1.010s	13.830us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	5.390s	134.864us	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	35.720s	877.717us	50	50	100.00
V2	lc_errors	lc_ctrl_errors	22.820s	560.638us	50	50	100.00
V2	security_escalation	lc_ctrl_state_failure	35.720s	877.717us	50	50	100.00
		lc_ctrl_prog_failure	5.390s	134.864us	50	50	100.00
		lc_ctrl_errors	22.820s	560.638us	50	50	100.00
		lc_ctrl_security_escalation	17.940s	555.368us	50	50	100.00
		lc_ctrl_jtag_state_failure	2.124m	3.966ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	19.270s	5.821ms	20	20	100.00
		lc_ctrl_jtag_errors	1.881m	68.916ms	20	20	100.00
V2	jtag_access	lc_ctrl_jtag_smoke	13.380s	449.395us	20	20	100.00
		lc_ctrl_jtag_state_post_trans	25.290s	1.567ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	19.270s	5.821ms	20	20	100.00
		lc_ctrl_jtag_errors	1.881m	68.916ms	20	20	100.00
		lc_ctrl_jtag_access	24.270s	1.068ms	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	36.900s	9.481ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	4.330s	634.981us	10	10	100.00
		lc_ctrl_jtag_csr_rw	3.170s	108.295us	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	45.560s	11.002ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	26.680s	1.240ms	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	1.960s	271.223us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	5.100s	745.472us	10	10	100.00
		lc_ctrl_jtag_alert_test	4.050s	172.479us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	14.780s	1.957ms	10	10	100.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.190s	34.785us	50	50	100.00
V2	stress_all	lc_ctrl_stress_all	10.018m	18.534ms	49	50	98.00
V2	alert_test	lc_ctrl_alert_test	1.600s	168.075us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	5.900s	579.985us	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	5.900s	579.985us	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.280s	17.705us	5	5	100.00
		lc_ctrl_csr_rw	1.210s	17.121us	20	20	100.00
		lc_ctrl_csr_aliasing	1.550s	279.809us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.980s	195.478us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.280s	17.705us	5	5	100.00
		lc_ctrl_csr_rw	1.210s	17.121us	20	20	100.00
		lc_ctrl_csr_aliasing	1.550s	279.809us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.980s	195.478us	20	20	100.00
V2		TOTAL			699	700	99.86
V2S	tl_intg_err	lc_ctrl_sec_cm	39.620s	912.495us	5	5	100.00
		lc_ctrl_tl_intg_err	4.760s	838.709us	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	4.760s	838.709us	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	25.600s	3.165ms	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	35.720s	877.717us	50	50	100.00
		lc_ctrl_sec_cm	39.620s	912.495us	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	35.720s	877.717us	50	50	100.00
		lc_ctrl_sec_cm	39.620s	912.495us	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	35.720s	877.717us	50	50	100.00
		lc_ctrl_sec_cm	39.620s	912.495us	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	35.720s	877.717us	50	50	100.00
		lc_ctrl_sec_cm	39.620s	912.495us	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	35.720s	877.717us	50	50	100.00
		lc_ctrl_sec_cm	39.620s	912.495us	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	35.720s	877.717us	50	50	100.00
		lc_ctrl_sec_cm	39.620s	912.495us	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	35.720s	877.717us	50	50	100.00
		lc_ctrl_sec_cm	39.620s	912.495us	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	35.720s	877.717us	50	50	100.00
		lc_ctrl_sec_cm	39.620s	912.495us	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	17.940s	555.368us	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	10.480s	147.179us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	25.290s	1.567ms	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	21.920s	3.188ms	38	50	76.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	21.920s	3.188ms	38	50	76.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	21.250s	11.280ms	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	18.000s	2.192ms	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	18.000s	2.192ms	50	50	100.00
V2S		TOTAL			163	175	93.14
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	29.419m	78.095ms	21	50	42.00
V3		TOTAL			21	50	42.00
		TOTAL			988	1030	95.92

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	26	96.30
V2S	5	5	4	80.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.23	97.92	95.84	93.38	100.00	98.52	99.00	95.94

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:825) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 19 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 19 failures.

    • 4.lc_ctrl_stress_all_with_rand_reset.12142629333672914379112434116284452927330046309802194867399593919072554420
      Line 22059, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/4.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 15203167228 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 15203167228 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 6.lc_ctrl_stress_all_with_rand_reset.107433619603819975064592453275973442335808810382038556677953267882853538268273
      Line 26214, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/6.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 56628831320 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 56628831320 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 17 more failures.

• UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_sec_mubi_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (* [*] vs * [*]) has 12 failures:

  • Test lc_ctrl_sec_mubi has 12 failures.

    • 2.lc_ctrl_sec_mubi.19578155680268731993878703000056496497758350013645223808853172688023743026452
      Line 1712, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/2.lc_ctrl_sec_mubi/latest/run.log

        UVM_ERROR @ 111755629 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_sec_mubi_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 111755629 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 6.lc_ctrl_sec_mubi.103173007531030644734763188025377457306875922880699513569159997357652142682304
      Line 3620, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/6.lc_ctrl_sec_mubi/latest/run.log

        UVM_ERROR @ 1383711616 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_sec_mubi_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 1383711616 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 10 more failures.

• UVM_ERROR (cip_base_scoreboard.sv:301) scoreboard [scoreboard] alert fatal_prog_error did not trigger max_delay:* has 5 failures:

  • Test lc_ctrl_stress_all has 1 failures.

    • 13.lc_ctrl_stress_all.33399252973247094607328700971070201293738520447040391112118157504132638535877
      Line 13278, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/13.lc_ctrl_stress_all/latest/run.log

        UVM_ERROR @ 6143327898 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 6143327898 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test lc_ctrl_stress_all_with_rand_reset has 4 failures.

    • 24.lc_ctrl_stress_all_with_rand_reset.71743782609562063425768903585102155951491658824933890320469566975138937036450
      Line 14316, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/24.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 62268502451 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 62268502451 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 32.lc_ctrl_stress_all_with_rand_reset.111576367382218282589552202960985506180219461154772761572535704353712622913275
      Line 42121, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/32.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 131463457689 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 131463457689 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 2 more failures.

• UVM_ERROR (cip_base_vseq.sv:551) [lc_ctrl_common_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_state_error fired unexpectedly! has 2 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 2 failures.

    • 13.lc_ctrl_stress_all_with_rand_reset.104333401254785338927034248098565880512099895208193193262112990305365477830180
      Line 25439, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/13.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 111196673645 ps: (cip_base_vseq.sv:551) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
        UVM_INFO @ 111196673645 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 35.lc_ctrl_stress_all_with_rand_reset.44917010215416757593618447080248113565574518548417074330115904808306979693504
      Line 43794, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/35.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 44528590862 ps: (cip_base_vseq.sv:551) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
        UVM_INFO @ 44528590862 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Error-[CNST-STOF] Constraint solver timeout failure has 2 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 2 failures.

    • 25.lc_ctrl_stress_all_with_rand_reset.85126230723004167610934116234530494853687085021555708727680622724519624927031
      Line 38802, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/25.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        Error-[CNST-STOF] Constraint solver timeout failure
        ../src/lowrisc_dv_sec_cm_0/prim_sparse_fsm_flop_if.sv, 43
          Exceeded cpu time limit during solve.
          Please use the run-time switch +ntb_solver_cpu_limit to increase the cpu
          limit.  The default cpu limit is 1000 seconds per partition.
      

    • 44.lc_ctrl_stress_all_with_rand_reset.63800296723564193272600822976188741747528444646709032817367062045253449082543
      Line 40342, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/44.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        Error-[CNST-STOF] Constraint solver timeout failure
        ../src/lowrisc_dv_sec_cm_0/prim_sparse_fsm_flop_if.sv, 43
          Exceeded cpu time limit during solve.
          Please use the run-time switch +ntb_solver_cpu_limit to increase the cpu
          limit.  The default cpu limit is 1000 seconds per partition.
      

• Job lc_ctrl_volatile_unlock_disabled-sim-vcs_run_default killed due to: Exit reason: Job failed: the job consumes more ram than allocated, try to request more ram for the job. has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 0.lc_ctrl_stress_all_with_rand_reset.60370102870689756557115604405186934336570233221820836339575188533086720413461
      Log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/0.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        Job ID: smart:8b906f40-27c6-4e20-abcd-2e809973b465
      

• UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (* [*] vs * [*]) has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 17.lc_ctrl_stress_all_with_rand_reset.3601364163620924433091209964063593820535295523329376423395950015800831939960
      Line 16358, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/17.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 13512353357 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 13512353357 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

• Latest
• 2024.07.10_10.42.36
• 2024.07.08_10.12.42
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