LC_CTRL/VOLATILE_UNLOCK_DISABLED Simulation Results

Thursday July 11 2024 23:02:31 UTC

GitHub Revision: edf2fd5092

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 110991919330983905489672005724934609038320729526710604109871030362225161447318

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	13.230s	1.953ms	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.240s	65.653us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.140s	33.092us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	1.920s	97.677us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	1.600s	102.032us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	1.860s	24.288us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.140s	33.092us	20	20	100.00
		lc_ctrl_csr_aliasing	1.600s	102.032us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	10.370s	119.876us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	17.780s	531.585us	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	1.010s	13.801us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	5.060s	111.977us	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	40.370s	324.992us	50	50	100.00
V2	lc_errors	lc_ctrl_errors	18.790s	2.601ms	50	50	100.00
V2	security_escalation	lc_ctrl_state_failure	40.370s	324.992us	50	50	100.00
		lc_ctrl_prog_failure	5.060s	111.977us	50	50	100.00
		lc_ctrl_errors	18.790s	2.601ms	50	50	100.00
		lc_ctrl_security_escalation	18.410s	540.815us	50	50	100.00
		lc_ctrl_jtag_state_failure	1.497m	4.856ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	14.980s	2.013ms	20	20	100.00
		lc_ctrl_jtag_errors	1.946m	4.508ms	20	20	100.00
V2	jtag_access	lc_ctrl_jtag_smoke	18.650s	775.030us	20	20	100.00
		lc_ctrl_jtag_state_post_trans	32.760s	1.159ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	14.980s	2.013ms	20	20	100.00
		lc_ctrl_jtag_errors	1.946m	4.508ms	20	20	100.00
		lc_ctrl_jtag_access	34.880s	1.493ms	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	33.660s	1.112ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	3.610s	118.754us	10	10	100.00
		lc_ctrl_jtag_csr_rw	4.290s	191.331us	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	45.940s	2.219ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	17.710s	14.883ms	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	2.060s	47.960us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	4.090s	263.561us	10	10	100.00
		lc_ctrl_jtag_alert_test	2.800s	98.566us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	16.950s	4.694ms	10	10	100.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.390s	18.629us	50	50	100.00
V2	stress_all	lc_ctrl_stress_all	9.686m	75.224ms	50	50	100.00
V2	alert_test	lc_ctrl_alert_test	1.430s	106.147us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	4.550s	437.593us	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	4.550s	437.593us	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.240s	65.653us	5	5	100.00
		lc_ctrl_csr_rw	1.140s	33.092us	20	20	100.00
		lc_ctrl_csr_aliasing	1.600s	102.032us	5	5	100.00
		lc_ctrl_same_csr_outstanding	2.150s	81.940us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.240s	65.653us	5	5	100.00
		lc_ctrl_csr_rw	1.140s	33.092us	20	20	100.00
		lc_ctrl_csr_aliasing	1.600s	102.032us	5	5	100.00
		lc_ctrl_same_csr_outstanding	2.150s	81.940us	20	20	100.00
V2		TOTAL			700	700	100.00
V2S	tl_intg_err	lc_ctrl_sec_cm	38.940s	1.124ms	5	5	100.00
		lc_ctrl_tl_intg_err	4.160s	111.486us	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	4.160s	111.486us	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	17.780s	531.585us	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	40.370s	324.992us	50	50	100.00
		lc_ctrl_sec_cm	38.940s	1.124ms	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	40.370s	324.992us	50	50	100.00
		lc_ctrl_sec_cm	38.940s	1.124ms	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	40.370s	324.992us	50	50	100.00
		lc_ctrl_sec_cm	38.940s	1.124ms	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	40.370s	324.992us	50	50	100.00
		lc_ctrl_sec_cm	38.940s	1.124ms	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	40.370s	324.992us	50	50	100.00
		lc_ctrl_sec_cm	38.940s	1.124ms	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	40.370s	324.992us	50	50	100.00
		lc_ctrl_sec_cm	38.940s	1.124ms	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	40.370s	324.992us	50	50	100.00
		lc_ctrl_sec_cm	38.940s	1.124ms	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	40.370s	324.992us	50	50	100.00
		lc_ctrl_sec_cm	38.940s	1.124ms	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	18.410s	540.815us	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	10.370s	119.876us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	32.760s	1.159ms	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	21.730s	532.613us	38	50	76.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	21.730s	532.613us	38	50	76.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	22.800s	947.726us	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	14.870s	624.756us	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	14.870s	624.756us	50	50	100.00
V2S		TOTAL			163	175	93.14
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	1.003h	34.215ms	24	50	48.00
V3		TOTAL			24	50	48.00
		TOTAL			992	1030	96.31

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	27	100.00
V2S	5	5	4	80.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.89	97.92	95.75	93.38	97.62	98.52	98.76	96.29

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:825) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 21 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 21 failures.

    • 3.lc_ctrl_stress_all_with_rand_reset.95451717090766467239028997412119436665124548912545828952385961682719406822390
      Line 1234, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/3.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 8158698833 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 8158698833 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 6.lc_ctrl_stress_all_with_rand_reset.73056094599185191994811817038948762981218552462907158417093706932370255671359
      Line 7806, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/6.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 7469540384 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 7469540384 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 19 more failures.

• UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_sec_mubi_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (* [*] vs * [*]) has 12 failures:

  • Test lc_ctrl_sec_mubi has 12 failures.

    • 0.lc_ctrl_sec_mubi.4559377159568654403492579616067979595046611751833521247051118160293083306055
      Line 1856, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/0.lc_ctrl_sec_mubi/latest/run.log

        UVM_ERROR @ 313005366 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_sec_mubi_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 313005366 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 2.lc_ctrl_sec_mubi.37622148008464149239956203671456419839025083200904164341186081659750052060205
      Line 1042, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/2.lc_ctrl_sec_mubi/latest/run.log

        UVM_ERROR @ 208969026 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_sec_mubi_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 208969026 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 10 more failures.

• UVM_ERROR (cip_base_scoreboard.sv:301) scoreboard [scoreboard] alert fatal_prog_error did not trigger max_delay:* has 3 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 3 failures.

    • 12.lc_ctrl_stress_all_with_rand_reset.82425062411986115703586358849810278721400551296960130105691129965573926358559
      Line 45385, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/12.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 34215155395 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 34215155395 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 25.lc_ctrl_stress_all_with_rand_reset.92963687019091302214964518054210440873892984027436634314940965676880936958851
      Line 24544, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/25.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 13796877713 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 13796877713 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 1 more failures.

• Error-[CNST-STOF] Constraint solver timeout failure has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 10.lc_ctrl_stress_all_with_rand_reset.108065509349656191283664309064130811846073579322391710503782718898041935338599
      Line 50092, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/10.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        Error-[CNST-STOF] Constraint solver timeout failure
        ../src/lowrisc_dv_sec_cm_0/prim_sparse_fsm_flop_if.sv, 43
          Exceeded cpu time limit during solve.
          Please use the run-time switch +ntb_solver_cpu_limit to increase the cpu
          limit.  The default cpu limit is 1000 seconds per partition.
      

• UVM_ERROR (cip_base_vseq.sv:551) [lc_ctrl_common_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_state_error fired unexpectedly! has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 47.lc_ctrl_stress_all_with_rand_reset.86717177430455346986031920698960126151028899598040002841795237467878064114975
      Line 13869, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/47.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 8203425507 ps: (cip_base_vseq.sv:551) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
        UVM_INFO @ 8203425507 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

• Latest
• 2024.07.11_10.35.11
• 2024.07.10_10.42.36
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