LC_CTRL/VOLATILE_UNLOCK_DISABLED Simulation Results

Friday July 12 2024 23:02:19 UTC

GitHub Revision: 5967df933a

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 46476530947956470787268850137993439884379231200278174763551439909664842175844

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke lc_ctrl_smoke 5.680s 93.413us 50 50 100.00
V1 csr_hw_reset lc_ctrl_csr_hw_reset 1.280s 22.072us 5 5 100.00
V1 csr_rw lc_ctrl_csr_rw 1.240s 20.797us 20 20 100.00
V1 csr_bit_bash lc_ctrl_csr_bit_bash 2.090s 371.779us 5 5 100.00
V1 csr_aliasing lc_ctrl_csr_aliasing 1.800s 149.087us 5 5 100.00
V1 csr_mem_rw_with_rand_reset lc_ctrl_csr_mem_rw_with_rand_reset 1.700s 44.514us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr lc_ctrl_csr_rw 1.240s 20.797us 20 20 100.00
lc_ctrl_csr_aliasing 1.800s 149.087us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 state_post_trans lc_ctrl_state_post_trans 11.900s 405.261us 50 50 100.00
V2 regwen_during_op lc_ctrl_regwen_during_op 25.400s 375.526us 10 10 100.00
V2 rand_wr_claim_transition_if lc_ctrl_claim_transition_if 1.070s 13.263us 10 10 100.00
V2 lc_prog_failure lc_ctrl_prog_failure 4.780s 211.614us 50 50 100.00
V2 lc_state_failure lc_ctrl_state_failure 39.450s 1.395ms 50 50 100.00
V2 lc_errors lc_ctrl_errors 21.550s 864.225us 50 50 100.00
V2 security_escalation lc_ctrl_state_failure 39.450s 1.395ms 50 50 100.00
lc_ctrl_prog_failure 4.780s 211.614us 50 50 100.00
lc_ctrl_errors 21.550s 864.225us 50 50 100.00
lc_ctrl_security_escalation 18.510s 2.215ms 50 50 100.00
lc_ctrl_jtag_state_failure 1.485m 2.823ms 20 20 100.00
lc_ctrl_jtag_prog_failure 20.890s 3.256ms 20 20 100.00
lc_ctrl_jtag_errors 1.719m 3.771ms 20 20 100.00
V2 jtag_access lc_ctrl_jtag_smoke 18.560s 1.473ms 20 20 100.00
lc_ctrl_jtag_state_post_trans 36.240s 4.096ms 20 20 100.00
lc_ctrl_jtag_prog_failure 20.890s 3.256ms 20 20 100.00
lc_ctrl_jtag_errors 1.719m 3.771ms 20 20 100.00
lc_ctrl_jtag_access 21.990s 4.993ms 50 50 100.00
lc_ctrl_jtag_regwen_during_op 26.400s 912.490us 10 10 100.00
lc_ctrl_jtag_csr_hw_reset 3.080s 108.805us 10 10 100.00
lc_ctrl_jtag_csr_rw 3.280s 115.522us 10 10 100.00
lc_ctrl_jtag_csr_bit_bash 56.950s 2.600ms 10 10 100.00
lc_ctrl_jtag_csr_aliasing 22.970s 1.549ms 10 10 100.00
lc_ctrl_jtag_same_csr_outstanding 1.990s 162.075us 10 10 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 5.890s 873.341us 10 10 100.00
lc_ctrl_jtag_alert_test 2.860s 351.436us 10 10 100.00
V2 jtag_priority lc_ctrl_jtag_priority 36.340s 1.556ms 10 10 100.00
V2 lc_ctrl_volatile_unlock lc_ctrl_volatile_unlock_smoke 1.180s 60.307us 50 50 100.00
V2 stress_all lc_ctrl_stress_all 11.024m 44.920ms 50 50 100.00
V2 alert_test lc_ctrl_alert_test 1.300s 21.903us 50 50 100.00
V2 tl_d_oob_addr_access lc_ctrl_tl_errors 5.300s 397.370us 20 20 100.00
V2 tl_d_illegal_access lc_ctrl_tl_errors 5.300s 397.370us 20 20 100.00
V2 tl_d_outstanding_access lc_ctrl_csr_hw_reset 1.280s 22.072us 5 5 100.00
lc_ctrl_csr_rw 1.240s 20.797us 20 20 100.00
lc_ctrl_csr_aliasing 1.800s 149.087us 5 5 100.00
lc_ctrl_same_csr_outstanding 1.970s 44.546us 20 20 100.00
V2 tl_d_partial_access lc_ctrl_csr_hw_reset 1.280s 22.072us 5 5 100.00
lc_ctrl_csr_rw 1.240s 20.797us 20 20 100.00
lc_ctrl_csr_aliasing 1.800s 149.087us 5 5 100.00
lc_ctrl_same_csr_outstanding 1.970s 44.546us 20 20 100.00
V2 TOTAL 700 700 100.00
V2S tl_intg_err lc_ctrl_sec_cm 34.660s 873.399us 5 5 100.00
lc_ctrl_tl_intg_err 5.000s 622.624us 20 20 100.00
V2S sec_cm_bus_integrity lc_ctrl_tl_intg_err 5.000s 622.624us 20 20 100.00
V2S sec_cm_transition_config_regwen lc_ctrl_regwen_during_op 25.400s 375.526us 10 10 100.00
V2S sec_cm_manuf_state_sparse lc_ctrl_state_failure 39.450s 1.395ms 50 50 100.00
lc_ctrl_sec_cm 34.660s 873.399us 5 5 100.00
V2S sec_cm_transition_ctr_sparse lc_ctrl_state_failure 39.450s 1.395ms 50 50 100.00
lc_ctrl_sec_cm 34.660s 873.399us 5 5 100.00
V2S sec_cm_manuf_state_bkgn_chk lc_ctrl_state_failure 39.450s 1.395ms 50 50 100.00
lc_ctrl_sec_cm 34.660s 873.399us 5 5 100.00
V2S sec_cm_transition_ctr_bkgn_chk lc_ctrl_state_failure 39.450s 1.395ms 50 50 100.00
lc_ctrl_sec_cm 34.660s 873.399us 5 5 100.00
V2S sec_cm_state_config_sparse lc_ctrl_state_failure 39.450s 1.395ms 50 50 100.00
lc_ctrl_sec_cm 34.660s 873.399us 5 5 100.00
V2S sec_cm_main_fsm_sparse lc_ctrl_state_failure 39.450s 1.395ms 50 50 100.00
lc_ctrl_sec_cm 34.660s 873.399us 5 5 100.00
V2S sec_cm_kmac_fsm_sparse lc_ctrl_state_failure 39.450s 1.395ms 50 50 100.00
lc_ctrl_sec_cm 34.660s 873.399us 5 5 100.00
V2S sec_cm_main_fsm_local_esc lc_ctrl_state_failure 39.450s 1.395ms 50 50 100.00
lc_ctrl_sec_cm 34.660s 873.399us 5 5 100.00
V2S sec_cm_main_fsm_global_esc lc_ctrl_security_escalation 18.510s 2.215ms 50 50 100.00
V2S sec_cm_main_ctrl_flow_consistency lc_ctrl_state_post_trans 11.900s 405.261us 50 50 100.00
lc_ctrl_jtag_state_post_trans 36.240s 4.096ms 20 20 100.00
V2S sec_cm_intersig_mubi lc_ctrl_sec_mubi 21.620s 1.470ms 40 50 80.00
V2S sec_cm_token_valid_ctrl_mubi lc_ctrl_sec_mubi 21.620s 1.470ms 40 50 80.00
V2S sec_cm_token_digest lc_ctrl_sec_token_digest 23.690s 11.115ms 50 50 100.00
V2S sec_cm_token_mux_ctrl_redun lc_ctrl_sec_token_mux 19.580s 2.468ms 50 50 100.00
V2S sec_cm_token_valid_mux_redun lc_ctrl_sec_token_mux 19.580s 2.468ms 50 50 100.00
V2S TOTAL 165 175 94.29
V3 stress_all_with_rand_reset lc_ctrl_stress_all_with_rand_reset 29.014m 68.548ms 20 50 40.00
V3 TOTAL 20 50 40.00
TOTAL 990 1030 96.12

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 27 27 27 100.00
V2S 5 5 4 80.00
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
96.89 97.92 96.12 93.38 97.62 98.52 98.76 95.94

Failure Buckets

Past Results