5967df933a
Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
---|---|---|---|---|---|---|---|
V1 | smoke | lc_ctrl_smoke | 5.680s | 93.413us | 50 | 50 | 100.00 |
V1 | csr_hw_reset | lc_ctrl_csr_hw_reset | 1.280s | 22.072us | 5 | 5 | 100.00 |
V1 | csr_rw | lc_ctrl_csr_rw | 1.240s | 20.797us | 20 | 20 | 100.00 |
V1 | csr_bit_bash | lc_ctrl_csr_bit_bash | 2.090s | 371.779us | 5 | 5 | 100.00 |
V1 | csr_aliasing | lc_ctrl_csr_aliasing | 1.800s | 149.087us | 5 | 5 | 100.00 |
V1 | csr_mem_rw_with_rand_reset | lc_ctrl_csr_mem_rw_with_rand_reset | 1.700s | 44.514us | 20 | 20 | 100.00 |
V1 | regwen_csr_and_corresponding_lockable_csr | lc_ctrl_csr_rw | 1.240s | 20.797us | 20 | 20 | 100.00 |
lc_ctrl_csr_aliasing | 1.800s | 149.087us | 5 | 5 | 100.00 | ||
V1 | TOTAL | 105 | 105 | 100.00 | |||
V2 | state_post_trans | lc_ctrl_state_post_trans | 11.900s | 405.261us | 50 | 50 | 100.00 |
V2 | regwen_during_op | lc_ctrl_regwen_during_op | 25.400s | 375.526us | 10 | 10 | 100.00 |
V2 | rand_wr_claim_transition_if | lc_ctrl_claim_transition_if | 1.070s | 13.263us | 10 | 10 | 100.00 |
V2 | lc_prog_failure | lc_ctrl_prog_failure | 4.780s | 211.614us | 50 | 50 | 100.00 |
V2 | lc_state_failure | lc_ctrl_state_failure | 39.450s | 1.395ms | 50 | 50 | 100.00 |
V2 | lc_errors | lc_ctrl_errors | 21.550s | 864.225us | 50 | 50 | 100.00 |
V2 | security_escalation | lc_ctrl_state_failure | 39.450s | 1.395ms | 50 | 50 | 100.00 |
lc_ctrl_prog_failure | 4.780s | 211.614us | 50 | 50 | 100.00 | ||
lc_ctrl_errors | 21.550s | 864.225us | 50 | 50 | 100.00 | ||
lc_ctrl_security_escalation | 18.510s | 2.215ms | 50 | 50 | 100.00 | ||
lc_ctrl_jtag_state_failure | 1.485m | 2.823ms | 20 | 20 | 100.00 | ||
lc_ctrl_jtag_prog_failure | 20.890s | 3.256ms | 20 | 20 | 100.00 | ||
lc_ctrl_jtag_errors | 1.719m | 3.771ms | 20 | 20 | 100.00 | ||
V2 | jtag_access | lc_ctrl_jtag_smoke | 18.560s | 1.473ms | 20 | 20 | 100.00 |
lc_ctrl_jtag_state_post_trans | 36.240s | 4.096ms | 20 | 20 | 100.00 | ||
lc_ctrl_jtag_prog_failure | 20.890s | 3.256ms | 20 | 20 | 100.00 | ||
lc_ctrl_jtag_errors | 1.719m | 3.771ms | 20 | 20 | 100.00 | ||
lc_ctrl_jtag_access | 21.990s | 4.993ms | 50 | 50 | 100.00 | ||
lc_ctrl_jtag_regwen_during_op | 26.400s | 912.490us | 10 | 10 | 100.00 | ||
lc_ctrl_jtag_csr_hw_reset | 3.080s | 108.805us | 10 | 10 | 100.00 | ||
lc_ctrl_jtag_csr_rw | 3.280s | 115.522us | 10 | 10 | 100.00 | ||
lc_ctrl_jtag_csr_bit_bash | 56.950s | 2.600ms | 10 | 10 | 100.00 | ||
lc_ctrl_jtag_csr_aliasing | 22.970s | 1.549ms | 10 | 10 | 100.00 | ||
lc_ctrl_jtag_same_csr_outstanding | 1.990s | 162.075us | 10 | 10 | 100.00 | ||
lc_ctrl_jtag_csr_mem_rw_with_rand_reset | 5.890s | 873.341us | 10 | 10 | 100.00 | ||
lc_ctrl_jtag_alert_test | 2.860s | 351.436us | 10 | 10 | 100.00 | ||
V2 | jtag_priority | lc_ctrl_jtag_priority | 36.340s | 1.556ms | 10 | 10 | 100.00 |
V2 | lc_ctrl_volatile_unlock | lc_ctrl_volatile_unlock_smoke | 1.180s | 60.307us | 50 | 50 | 100.00 |
V2 | stress_all | lc_ctrl_stress_all | 11.024m | 44.920ms | 50 | 50 | 100.00 |
V2 | alert_test | lc_ctrl_alert_test | 1.300s | 21.903us | 50 | 50 | 100.00 |
V2 | tl_d_oob_addr_access | lc_ctrl_tl_errors | 5.300s | 397.370us | 20 | 20 | 100.00 |
V2 | tl_d_illegal_access | lc_ctrl_tl_errors | 5.300s | 397.370us | 20 | 20 | 100.00 |
V2 | tl_d_outstanding_access | lc_ctrl_csr_hw_reset | 1.280s | 22.072us | 5 | 5 | 100.00 |
lc_ctrl_csr_rw | 1.240s | 20.797us | 20 | 20 | 100.00 | ||
lc_ctrl_csr_aliasing | 1.800s | 149.087us | 5 | 5 | 100.00 | ||
lc_ctrl_same_csr_outstanding | 1.970s | 44.546us | 20 | 20 | 100.00 | ||
V2 | tl_d_partial_access | lc_ctrl_csr_hw_reset | 1.280s | 22.072us | 5 | 5 | 100.00 |
lc_ctrl_csr_rw | 1.240s | 20.797us | 20 | 20 | 100.00 | ||
lc_ctrl_csr_aliasing | 1.800s | 149.087us | 5 | 5 | 100.00 | ||
lc_ctrl_same_csr_outstanding | 1.970s | 44.546us | 20 | 20 | 100.00 | ||
V2 | TOTAL | 700 | 700 | 100.00 | |||
V2S | tl_intg_err | lc_ctrl_sec_cm | 34.660s | 873.399us | 5 | 5 | 100.00 |
lc_ctrl_tl_intg_err | 5.000s | 622.624us | 20 | 20 | 100.00 | ||
V2S | sec_cm_bus_integrity | lc_ctrl_tl_intg_err | 5.000s | 622.624us | 20 | 20 | 100.00 |
V2S | sec_cm_transition_config_regwen | lc_ctrl_regwen_during_op | 25.400s | 375.526us | 10 | 10 | 100.00 |
V2S | sec_cm_manuf_state_sparse | lc_ctrl_state_failure | 39.450s | 1.395ms | 50 | 50 | 100.00 |
lc_ctrl_sec_cm | 34.660s | 873.399us | 5 | 5 | 100.00 | ||
V2S | sec_cm_transition_ctr_sparse | lc_ctrl_state_failure | 39.450s | 1.395ms | 50 | 50 | 100.00 |
lc_ctrl_sec_cm | 34.660s | 873.399us | 5 | 5 | 100.00 | ||
V2S | sec_cm_manuf_state_bkgn_chk | lc_ctrl_state_failure | 39.450s | 1.395ms | 50 | 50 | 100.00 |
lc_ctrl_sec_cm | 34.660s | 873.399us | 5 | 5 | 100.00 | ||
V2S | sec_cm_transition_ctr_bkgn_chk | lc_ctrl_state_failure | 39.450s | 1.395ms | 50 | 50 | 100.00 |
lc_ctrl_sec_cm | 34.660s | 873.399us | 5 | 5 | 100.00 | ||
V2S | sec_cm_state_config_sparse | lc_ctrl_state_failure | 39.450s | 1.395ms | 50 | 50 | 100.00 |
lc_ctrl_sec_cm | 34.660s | 873.399us | 5 | 5 | 100.00 | ||
V2S | sec_cm_main_fsm_sparse | lc_ctrl_state_failure | 39.450s | 1.395ms | 50 | 50 | 100.00 |
lc_ctrl_sec_cm | 34.660s | 873.399us | 5 | 5 | 100.00 | ||
V2S | sec_cm_kmac_fsm_sparse | lc_ctrl_state_failure | 39.450s | 1.395ms | 50 | 50 | 100.00 |
lc_ctrl_sec_cm | 34.660s | 873.399us | 5 | 5 | 100.00 | ||
V2S | sec_cm_main_fsm_local_esc | lc_ctrl_state_failure | 39.450s | 1.395ms | 50 | 50 | 100.00 |
lc_ctrl_sec_cm | 34.660s | 873.399us | 5 | 5 | 100.00 | ||
V2S | sec_cm_main_fsm_global_esc | lc_ctrl_security_escalation | 18.510s | 2.215ms | 50 | 50 | 100.00 |
V2S | sec_cm_main_ctrl_flow_consistency | lc_ctrl_state_post_trans | 11.900s | 405.261us | 50 | 50 | 100.00 |
lc_ctrl_jtag_state_post_trans | 36.240s | 4.096ms | 20 | 20 | 100.00 | ||
V2S | sec_cm_intersig_mubi | lc_ctrl_sec_mubi | 21.620s | 1.470ms | 40 | 50 | 80.00 |
V2S | sec_cm_token_valid_ctrl_mubi | lc_ctrl_sec_mubi | 21.620s | 1.470ms | 40 | 50 | 80.00 |
V2S | sec_cm_token_digest | lc_ctrl_sec_token_digest | 23.690s | 11.115ms | 50 | 50 | 100.00 |
V2S | sec_cm_token_mux_ctrl_redun | lc_ctrl_sec_token_mux | 19.580s | 2.468ms | 50 | 50 | 100.00 |
V2S | sec_cm_token_valid_mux_redun | lc_ctrl_sec_token_mux | 19.580s | 2.468ms | 50 | 50 | 100.00 |
V2S | TOTAL | 165 | 175 | 94.29 | |||
V3 | stress_all_with_rand_reset | lc_ctrl_stress_all_with_rand_reset | 29.014m | 68.548ms | 20 | 50 | 40.00 |
V3 | TOTAL | 20 | 50 | 40.00 | |||
TOTAL | 990 | 1030 | 96.12 |
Items | Total | Written | Passing | Progress |
---|---|---|---|---|
V1 | 6 | 6 | 6 | 100.00 |
V2 | 27 | 27 | 27 | 100.00 |
V2S | 5 | 5 | 4 | 80.00 |
V3 | 1 | 1 | 0 | 0.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
---|---|---|---|---|---|---|---|
96.89 | 97.92 | 96.12 | 93.38 | 97.62 | 98.52 | 98.76 | 95.94 |
UVM_ERROR (cip_base_vseq.sv:825) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
has 23 failures:
2.lc_ctrl_stress_all_with_rand_reset.109007616654219407725486859863285839003955648497591679937888093280872359947184
Line 25856, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/2.lc_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 104387617051 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 104387617051 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
4.lc_ctrl_stress_all_with_rand_reset.40010088532203715079106247212892021933105731993711860548497434759909856267181
Line 12288, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/4.lc_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 9365942588 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 9365942588 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 21 more failures.
UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_sec_mubi_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (* [*] vs * [*])
has 10 failures:
5.lc_ctrl_sec_mubi.99966913975574947361794688553940974158873157275343966807988588092238692903029
Line 1226, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/5.lc_ctrl_sec_mubi/latest/run.log
UVM_ERROR @ 704961721 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_sec_mubi_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
UVM_INFO @ 704961721 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
7.lc_ctrl_sec_mubi.41486603233899466852179551762764338158694084350821207638760801096741193459208
Line 1986, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/7.lc_ctrl_sec_mubi/latest/run.log
UVM_ERROR @ 712075499 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_sec_mubi_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
UVM_INFO @ 712075499 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 8 more failures.
Error-[CNST-STOF] Constraint solver timeout failure
has 3 failures:
22.lc_ctrl_stress_all_with_rand_reset.87486310215940148458967734231674708946811836079134748407061021439500547433888
Line 43718, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/22.lc_ctrl_stress_all_with_rand_reset/latest/run.log
Error-[CNST-STOF] Constraint solver timeout failure
../src/lowrisc_dv_sec_cm_0/prim_sparse_fsm_flop_if.sv, 43
Exceeded cpu time limit during solve.
Please use the run-time switch +ntb_solver_cpu_limit to increase the cpu
limit. The default cpu limit is 1000 seconds per partition.
34.lc_ctrl_stress_all_with_rand_reset.29290225679823489062838681217885017393235225518199916099022016291384726095997
Line 34689, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/34.lc_ctrl_stress_all_with_rand_reset/latest/run.log
Error-[CNST-STOF] Constraint solver timeout failure
../src/lowrisc_dv_sec_cm_0/prim_sparse_fsm_flop_if.sv, 43
Exceeded cpu time limit during solve.
Please use the run-time switch +ntb_solver_cpu_limit to increase the cpu
limit. The default cpu limit is 1000 seconds per partition.
... and 1 more failures.
UVM_ERROR (cip_base_scoreboard.sv:301) scoreboard [scoreboard] alert fatal_prog_error did not trigger max_delay:*
has 1 failures:
8.lc_ctrl_stress_all_with_rand_reset.18292958293814182206478233915213593582515606636015110046419024092875379344393
Line 14007, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/8.lc_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 14001390200 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
UVM_INFO @ 14001390200 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (* [*] vs * [*])
has 1 failures:
12.lc_ctrl_stress_all_with_rand_reset.94157828106641452382787461253966616299627389262832324802709421615902933892429
Line 5471, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/12.lc_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 6470132718 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
UVM_INFO @ 6470132718 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:551) [lc_ctrl_regwen_during_op_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_prog_error fired unexpectedly!
has 1 failures:
36.lc_ctrl_stress_all_with_rand_reset.5702570258875047305543415726921164536690689891759668047725350405360867053595
Line 20701, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/36.lc_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 34675269526 ps: (cip_base_vseq.sv:551) [uvm_test_top.env.virtual_sequencer.lc_ctrl_regwen_during_op_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_prog_error fired unexpectedly!
UVM_INFO @ 34675269526 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:551) [lc_ctrl_common_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_state_error fired unexpectedly!
has 1 failures:
47.lc_ctrl_stress_all_with_rand_reset.111574292447871370740242250046211029165963554472606018384876410540162358840303
Line 44388, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/47.lc_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 28609208388 ps: (cip_base_vseq.sv:551) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
UVM_INFO @ 28609208388 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---