LC_CTRL/VOLATILE_UNLOCK_DISABLED Simulation Results

Saturday July 13 2024 23:02:33 UTC

GitHub Revision: d51405297e

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 101086804359139103922259090811397817605469534164678958852189348539757618502888

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	10.510s	170.258us	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.260s	72.151us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.180s	15.513us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	3.490s	94.604us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	1.780s	75.257us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	1.750s	37.024us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.180s	15.513us	20	20	100.00
		lc_ctrl_csr_aliasing	1.780s	75.257us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	10.510s	454.042us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	22.170s	773.664us	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	1.000s	12.420us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	5.610s	265.504us	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	40.470s	7.225ms	50	50	100.00
V2	lc_errors	lc_ctrl_errors	24.120s	1.045ms	50	50	100.00
V2	security_escalation	lc_ctrl_state_failure	40.470s	7.225ms	50	50	100.00
		lc_ctrl_prog_failure	5.610s	265.504us	50	50	100.00
		lc_ctrl_errors	24.120s	1.045ms	50	50	100.00
		lc_ctrl_security_escalation	18.500s	985.320us	50	50	100.00
		lc_ctrl_jtag_state_failure	1.525m	19.473ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	20.200s	1.009ms	20	20	100.00
		lc_ctrl_jtag_errors	1.154m	9.840ms	20	20	100.00
V2	jtag_access	lc_ctrl_jtag_smoke	12.530s	436.173us	20	20	100.00
		lc_ctrl_jtag_state_post_trans	34.500s	17.555ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	20.200s	1.009ms	20	20	100.00
		lc_ctrl_jtag_errors	1.154m	9.840ms	20	20	100.00
		lc_ctrl_jtag_access	28.510s	4.878ms	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	36.280s	4.529ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	3.110s	105.525us	10	10	100.00
		lc_ctrl_jtag_csr_rw	3.940s	214.176us	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	23.320s	1.248ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	17.630s	15.518ms	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	2.150s	399.168us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	3.480s	1.017ms	10	10	100.00
		lc_ctrl_jtag_alert_test	2.630s	327.210us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	21.790s	1.677ms	10	10	100.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.200s	48.352us	50	50	100.00
V2	stress_all	lc_ctrl_stress_all	12.343m	74.329ms	49	50	98.00
V2	alert_test	lc_ctrl_alert_test	1.340s	29.518us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	5.410s	520.963us	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	5.410s	520.963us	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.260s	72.151us	5	5	100.00
		lc_ctrl_csr_rw	1.180s	15.513us	20	20	100.00
		lc_ctrl_csr_aliasing	1.780s	75.257us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.920s	223.544us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.260s	72.151us	5	5	100.00
		lc_ctrl_csr_rw	1.180s	15.513us	20	20	100.00
		lc_ctrl_csr_aliasing	1.780s	75.257us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.920s	223.544us	20	20	100.00
V2		TOTAL			699	700	99.86
V2S	tl_intg_err	lc_ctrl_sec_cm	34.640s	860.783us	5	5	100.00
		lc_ctrl_tl_intg_err	4.220s	445.516us	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	4.220s	445.516us	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	22.170s	773.664us	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	40.470s	7.225ms	50	50	100.00
		lc_ctrl_sec_cm	34.640s	860.783us	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	40.470s	7.225ms	50	50	100.00
		lc_ctrl_sec_cm	34.640s	860.783us	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	40.470s	7.225ms	50	50	100.00
		lc_ctrl_sec_cm	34.640s	860.783us	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	40.470s	7.225ms	50	50	100.00
		lc_ctrl_sec_cm	34.640s	860.783us	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	40.470s	7.225ms	50	50	100.00
		lc_ctrl_sec_cm	34.640s	860.783us	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	40.470s	7.225ms	50	50	100.00
		lc_ctrl_sec_cm	34.640s	860.783us	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	40.470s	7.225ms	50	50	100.00
		lc_ctrl_sec_cm	34.640s	860.783us	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	40.470s	7.225ms	50	50	100.00
		lc_ctrl_sec_cm	34.640s	860.783us	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	18.500s	985.320us	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	10.510s	454.042us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	34.500s	17.555ms	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	18.340s	5.153ms	36	50	72.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	18.340s	5.153ms	36	50	72.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	22.380s	864.943us	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	15.330s	2.041ms	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	15.330s	2.041ms	50	50	100.00
V2S		TOTAL			161	175	92.00
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	1.511h	43.510ms	23	50	46.00
V3		TOTAL			23	50	46.00
		TOTAL			988	1030	95.92

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	26	96.30
V2S	5	5	4	80.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.30	97.92	95.84	93.38	100.00	98.52	99.00	96.47

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:825) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 22 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 22 failures.

    • 2.lc_ctrl_stress_all_with_rand_reset.45171357746943688514823623322765198970093988510287802013433295247021851648935
      Line 13305, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/2.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 17379442044 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 17379442044 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 4.lc_ctrl_stress_all_with_rand_reset.55107133473223153815284315821200640702044064278983041648514123303860020022120
      Line 334, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/4.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1655842709 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 1655842709 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 20 more failures.

• UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_sec_mubi_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (* [*] vs * [*]) has 14 failures:

  • Test lc_ctrl_sec_mubi has 14 failures.

    • 0.lc_ctrl_sec_mubi.7615076375269107641869629778792769224689237061918117845427053354742470090747
      Line 1460, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/0.lc_ctrl_sec_mubi/latest/run.log

        UVM_ERROR @  85998920 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_sec_mubi_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
        UVM_INFO @  85998920 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 2.lc_ctrl_sec_mubi.92042467545823940599899575818996606680999340309815149014664293576111429262231
      Line 2100, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/2.lc_ctrl_sec_mubi/latest/run.log

        UVM_ERROR @ 711100126 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_sec_mubi_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 711100126 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 12 more failures.

• UVM_ERROR (cip_base_scoreboard.sv:301) scoreboard [scoreboard] alert fatal_prog_error did not trigger max_delay:* has 3 failures:

  • Test lc_ctrl_stress_all has 1 failures.

    • 15.lc_ctrl_stress_all.3787088608131056767656107907052104793586727206416628175011547400934888735521
      Line 11592, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/15.lc_ctrl_stress_all/latest/run.log

        UVM_ERROR @ 8407721582 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 8407721582 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test lc_ctrl_stress_all_with_rand_reset has 2 failures.

    • 24.lc_ctrl_stress_all_with_rand_reset.2710247835156096766463690294545982695253792078259476545841842563042337410914
      Line 6964, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/24.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 17913670625 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 17913670625 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 46.lc_ctrl_stress_all_with_rand_reset.15645750497400469823274240133177982326793963423031217182562540939680421005486
      Line 1572, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/46.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 7283804891 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 7283804891 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:551) [lc_ctrl_common_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_state_error fired unexpectedly! has 2 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 2 failures.

    • 25.lc_ctrl_stress_all_with_rand_reset.33164451337737924323567218165654369180973121207617904414098834876412397304953
      Line 40737, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/25.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 43510180693 ps: (cip_base_vseq.sv:551) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
        UVM_INFO @ 43510180693 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 37.lc_ctrl_stress_all_with_rand_reset.10083421683286980778227094340483123354445526771862698499303863592060928889647
      Line 31823, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/37.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 37247061446 ps: (cip_base_vseq.sv:551) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
        UVM_INFO @ 37247061446 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Error-[CNST-STOF] Constraint solver timeout failure has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 21.lc_ctrl_stress_all_with_rand_reset.20985985708910538731678383681218571266142339541288581573422610699272046021912
      Line 37067, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/21.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        Error-[CNST-STOF] Constraint solver timeout failure
        ../src/lowrisc_dv_sec_cm_0/prim_sparse_fsm_flop_if.sv, 43
          Exceeded cpu time limit during solve.
          Please use the run-time switch +ntb_solver_cpu_limit to increase the cpu
          limit.  The default cpu limit is 1000 seconds per partition.
      

Past Results

• Latest
• 2024.07.13_08.23.03
• 2024.07.12_09.09.29
• 2024.07.11_10.35.11
• 2024.07.10_10.42.36
• 2024.07.08_10.12.42
• 2024.07.07_10.35.12
• 2024.07.06_10.42.49