LC_CTRL/VOLATILE_UNLOCK_DISABLED Simulation Results

Sunday July 14 2024 23:02:31 UTC

GitHub Revision: `c04cc5d074`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 63544391231451201456762274895161998707503467555380647510071702152169450996489

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	7.160s	124.888us	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.270s	39.703us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.090s	14.617us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	3.230s	183.339us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	1.620s	163.391us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	2.210s	30.672us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.090s	14.617us	20	20	100.00
		lc_ctrl_csr_aliasing	1.620s	163.391us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	10.840s	377.118us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	20.610s	390.576us	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	0.910s	14.415us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	4.410s	193.397us	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	37.380s	311.726us	50	50	100.00
V2	lc_errors	lc_ctrl_errors	22.890s	1.556ms	49	50	98.00
V2	security_escalation	lc_ctrl_state_failure	37.380s	311.726us	50	50	100.00
		lc_ctrl_prog_failure	4.410s	193.397us	50	50	100.00
		lc_ctrl_errors	22.890s	1.556ms	49	50	98.00
		lc_ctrl_security_escalation	19.960s	620.663us	50	50	100.00
		lc_ctrl_jtag_state_failure	1.375m	2.332ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	14.860s	1.497ms	20	20	100.00
		lc_ctrl_jtag_errors	2.040m	4.436ms	20	20	100.00
V2	jtag_access	lc_ctrl_jtag_smoke	10.060s	1.422ms	20	20	100.00
		lc_ctrl_jtag_state_post_trans	22.940s	612.683us	20	20	100.00
		lc_ctrl_jtag_prog_failure	14.860s	1.497ms	20	20	100.00
		lc_ctrl_jtag_errors	2.040m	4.436ms	20	20	100.00
		lc_ctrl_jtag_access	20.160s	1.589ms	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	43.870s	1.583ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	4.380s	935.691us	10	10	100.00
		lc_ctrl_jtag_csr_rw	3.320s	411.381us	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	18.630s	701.225us	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	15.290s	2.546ms	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	1.400s	138.513us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	4.250s	135.302us	10	10	100.00
		lc_ctrl_jtag_alert_test	1.820s	217.339us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	44.590s	7.472ms	10	10	100.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.040s	12.865us	50	50	100.00
V2	stress_all	lc_ctrl_stress_all	8.825m	89.069ms	50	50	100.00
V2	alert_test	lc_ctrl_alert_test	1.660s	157.831us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	5.280s	2.431ms	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	5.280s	2.431ms	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.270s	39.703us	5	5	100.00
		lc_ctrl_csr_rw	1.090s	14.617us	20	20	100.00
		lc_ctrl_csr_aliasing	1.620s	163.391us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.950s	86.882us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.270s	39.703us	5	5	100.00
		lc_ctrl_csr_rw	1.090s	14.617us	20	20	100.00
		lc_ctrl_csr_aliasing	1.620s	163.391us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.950s	86.882us	20	20	100.00
V2		TOTAL			699	700	99.86
V2S	tl_intg_err	lc_ctrl_sec_cm	37.320s	2.972ms	5	5	100.00
		lc_ctrl_tl_intg_err	4.400s	224.991us	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	4.400s	224.991us	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	20.610s	390.576us	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	37.380s	311.726us	50	50	100.00
		lc_ctrl_sec_cm	37.320s	2.972ms	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	37.380s	311.726us	50	50	100.00
		lc_ctrl_sec_cm	37.320s	2.972ms	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	37.380s	311.726us	50	50	100.00
		lc_ctrl_sec_cm	37.320s	2.972ms	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	37.380s	311.726us	50	50	100.00
		lc_ctrl_sec_cm	37.320s	2.972ms	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	37.380s	311.726us	50	50	100.00
		lc_ctrl_sec_cm	37.320s	2.972ms	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	37.380s	311.726us	50	50	100.00
		lc_ctrl_sec_cm	37.320s	2.972ms	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	37.380s	311.726us	50	50	100.00
		lc_ctrl_sec_cm	37.320s	2.972ms	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	37.380s	311.726us	50	50	100.00
		lc_ctrl_sec_cm	37.320s	2.972ms	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	19.960s	620.663us	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	10.840s	377.118us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	22.940s	612.683us	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	26.040s	2.745ms	43	50	86.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	26.040s	2.745ms	43	50	86.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	17.980s	3.735ms	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	19.390s	638.060us	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	19.390s	638.060us	50	50	100.00
V2S		TOTAL			168	175	96.00
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	1.239h	33.501ms	22	50	44.00
V3		TOTAL			22	50	44.00
		TOTAL			994	1030	96.50

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	26	96.30
V2S	5	5	4	80.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.93	97.92	95.93	93.38	97.62	98.52	99.00	96.11

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:825) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 21 failures:
- Test lc_ctrl_stress_all_with_rand_reset has 21 failures.
  - 1.lc_ctrl_stress_all_with_rand_reset.15642115962451659436250302252989011635777315236845910130100014301054195319917
    Line 11689, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/1.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 56598824151 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 56598824151 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 4.lc_ctrl_stress_all_with_rand_reset.85820379076547394101233010815228941745540968521354208221277580479706623958930
    Line 14031, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/4.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 45946075837 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 45946075837 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 19 more failures.
UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_sec_mubi_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (* [*] vs * [*]) has 7 failures:
- Test lc_ctrl_sec_mubi has 7 failures.
  - 0.lc_ctrl_sec_mubi.96576204326531490590363202118773206243221771708309029251561993337627362848223
    Line 1446, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/0.lc_ctrl_sec_mubi/latest/run.log
```
  UVM_ERROR @ 967838557 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_sec_mubi_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 967838557 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 8.lc_ctrl_sec_mubi.72473390126485674097327700936417700437359681174943774510421077052775737163354
    Line 1186, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/8.lc_ctrl_sec_mubi/latest/run.log
```
  UVM_ERROR @  84489282 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_sec_mubi_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
  UVM_INFO @  84489282 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 5 more failures.
UVM_ERROR (cip_base_scoreboard.sv:301) scoreboard [scoreboard] alert fatal_prog_error did not trigger max_delay:* has 4 failures:
- Test lc_ctrl_stress_all_with_rand_reset has 4 failures.
  - 11.lc_ctrl_stress_all_with_rand_reset.22894625998790740685507112939107817886645016948299907354451087525378255224581
    Line 21789, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/11.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 21091482781 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
  UVM_INFO @ 21091482781 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 13.lc_ctrl_stress_all_with_rand_reset.62984706792916360742661318350534738079430394581410275373974844465080771496876
    Line 12745, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/13.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 26360579349 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
  UVM_INFO @ 26360579349 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.
Error-[CNST-STOF] Constraint solver timeout failure has 1 failures:
- Test lc_ctrl_stress_all_with_rand_reset has 1 failures.
  - 3.lc_ctrl_stress_all_with_rand_reset.45798632366529533829244726510935402306344782430241175643181141221790728865082
    Line 44601, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/3.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Error-[CNST-STOF] Constraint solver timeout failure
  ../src/lowrisc_dv_sec_cm_0/prim_sparse_fsm_flop_if.sv, 43
    Exceeded cpu time limit during solve.
    Please use the run-time switch +ntb_solver_cpu_limit to increase the cpu
    limit.  The default cpu limit is 1000 seconds per partition.
```
UVM_ERROR (lc_ctrl_errors_vseq.sv:769) [lc_ctrl_lc_errors_vseq] Check failed otp_error_act == otp_error_exp (* [*] vs * [*]) has 1 failures:
- Test lc_ctrl_errors has 1 failures.
  - 4.lc_ctrl_errors.37951486986943863938677127470682084318200818945568517004591492054930252942800
    Line 1092, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/4.lc_ctrl_errors/latest/run.log
```
  UVM_ERROR @  82117010 ps: (lc_ctrl_errors_vseq.sv:769) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed otp_error_act == otp_error_exp (0 [0x0] vs 1 [0x1])
  UVM_INFO @  82117010 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:749) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:
- Test lc_ctrl_stress_all_with_rand_reset has 1 failures.
  - 33.lc_ctrl_stress_all_with_rand_reset.59146805545178869159219741191870395931600026599589572896932378625099376065894
    Line 18803, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/33.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 9403744672 ps: (cip_base_vseq.sv:749) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 9403744672 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:551) [lc_ctrl_common_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_state_error fired unexpectedly! has 1 failures:
- Test lc_ctrl_stress_all_with_rand_reset has 1 failures.
  - 43.lc_ctrl_stress_all_with_rand_reset.44771043844199553517887473598724106066320427781796128425017495521208657813517
    Line 27850, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/43.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 36710898381 ps: (cip_base_vseq.sv:551) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
  UVM_INFO @ 36710898381 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

LC_CTRL/VOLATILE_UNLOCK_DISABLED Simulation Results

Sunday July 14 2024 23:02:31 UTC

GitHub Revision: c04cc5d074

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 63544391231451201456762274895161998707503467555380647510071702152169450996489

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `c04cc5d074`