LC_CTRL/VOLATILE_UNLOCK_DISABLED Simulation Results

Monday July 15 2024 23:02:37 UTC

GitHub Revision: a04e34f557

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 78455839157994684327892029952813991699715169368132023215715425571513813941951

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	10.360s	783.116us	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.090s	124.876us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.110s	30.458us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	2.520s	68.932us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	1.800s	35.820us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	1.660s	80.001us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.110s	30.458us	20	20	100.00
		lc_ctrl_csr_aliasing	1.800s	35.820us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	10.120s	97.740us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	30.230s	1.760ms	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	1.000s	13.124us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	4.830s	105.966us	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	34.320s	370.349us	50	50	100.00
V2	lc_errors	lc_ctrl_errors	21.080s	3.803ms	50	50	100.00
V2	security_escalation	lc_ctrl_state_failure	34.320s	370.349us	50	50	100.00
		lc_ctrl_prog_failure	4.830s	105.966us	50	50	100.00
		lc_ctrl_errors	21.080s	3.803ms	50	50	100.00
		lc_ctrl_security_escalation	17.110s	743.039us	50	50	100.00
		lc_ctrl_jtag_state_failure	1.878m	3.484ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	11.220s	330.068us	20	20	100.00
		lc_ctrl_jtag_errors	1.763m	39.082ms	20	20	100.00
V2	jtag_access	lc_ctrl_jtag_smoke	16.020s	1.074ms	20	20	100.00
		lc_ctrl_jtag_state_post_trans	34.410s	4.641ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	11.220s	330.068us	20	20	100.00
		lc_ctrl_jtag_errors	1.763m	39.082ms	20	20	100.00
		lc_ctrl_jtag_access	19.450s	805.841us	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	39.960s	1.264ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	6.530s	282.162us	10	10	100.00
		lc_ctrl_jtag_csr_rw	3.810s	145.599us	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	50.410s	9.738ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	24.220s	1.159ms	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	1.850s	41.835us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	5.960s	957.491us	10	10	100.00
		lc_ctrl_jtag_alert_test	3.290s	1.241ms	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	10.220s	3.409ms	10	10	100.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.130s	22.888us	50	50	100.00
V2	stress_all	lc_ctrl_stress_all	13.389m	135.902ms	49	50	98.00
V2	alert_test	lc_ctrl_alert_test	2.100s	252.422us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	5.630s	333.630us	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	5.630s	333.630us	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.090s	124.876us	5	5	100.00
		lc_ctrl_csr_rw	1.110s	30.458us	20	20	100.00
		lc_ctrl_csr_aliasing	1.800s	35.820us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.500s	31.061us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.090s	124.876us	5	5	100.00
		lc_ctrl_csr_rw	1.110s	30.458us	20	20	100.00
		lc_ctrl_csr_aliasing	1.800s	35.820us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.500s	31.061us	20	20	100.00
V2		TOTAL			699	700	99.86
V2S	tl_intg_err	lc_ctrl_sec_cm	37.610s	724.638us	5	5	100.00
		lc_ctrl_tl_intg_err	4.180s	118.511us	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	4.180s	118.511us	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	30.230s	1.760ms	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	34.320s	370.349us	50	50	100.00
		lc_ctrl_sec_cm	37.610s	724.638us	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	34.320s	370.349us	50	50	100.00
		lc_ctrl_sec_cm	37.610s	724.638us	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	34.320s	370.349us	50	50	100.00
		lc_ctrl_sec_cm	37.610s	724.638us	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	34.320s	370.349us	50	50	100.00
		lc_ctrl_sec_cm	37.610s	724.638us	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	34.320s	370.349us	50	50	100.00
		lc_ctrl_sec_cm	37.610s	724.638us	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	34.320s	370.349us	50	50	100.00
		lc_ctrl_sec_cm	37.610s	724.638us	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	34.320s	370.349us	50	50	100.00
		lc_ctrl_sec_cm	37.610s	724.638us	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	34.320s	370.349us	50	50	100.00
		lc_ctrl_sec_cm	37.610s	724.638us	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	17.110s	743.039us	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	10.120s	97.740us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	34.410s	4.641ms	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	24.020s	560.804us	43	50	86.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	24.020s	560.804us	43	50	86.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	28.230s	4.561ms	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	20.070s	563.066us	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	20.070s	563.066us	50	50	100.00
V2S		TOTAL			168	175	96.00
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	1.634h	20.978ms	20	50	40.00
V3		TOTAL			20	50	40.00
		TOTAL			992	1030	96.31

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	26	96.30
V2S	5	5	4	80.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.92	97.97	96.03	93.40	97.62	98.73	98.76	95.94

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:825) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 24 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 24 failures.

    • 0.lc_ctrl_stress_all_with_rand_reset.2623605744790673945021860943820385544738882845920045254143213282141940011412
      Line 40624, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/0.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 264247251094 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10009 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 264247251094 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 1.lc_ctrl_stress_all_with_rand_reset.55620327788261116298431122960383945302291158656565208385169640489170767959613
      Line 3093, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/1.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 2967372764 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 2967372764 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 22 more failures.

• UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_sec_mubi_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (* [*] vs * [*]) has 7 failures:

  • Test lc_ctrl_sec_mubi has 7 failures.

    • 5.lc_ctrl_sec_mubi.72384294757348716423700001733514360486647693847101507501331128628433343033468
      Line 1550, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/5.lc_ctrl_sec_mubi/latest/run.log

        UVM_ERROR @ 1896855309 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_sec_mubi_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 1896855309 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 7.lc_ctrl_sec_mubi.100798281788604682936376756294899732099517843575603028136851826584107597496829
      Line 4130, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/7.lc_ctrl_sec_mubi/latest/run.log

        UVM_ERROR @ 837460339 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_sec_mubi_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 837460339 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 5 more failures.

• Error-[CNST-STOF] Constraint solver timeout failure has 3 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 3 failures.

    • 3.lc_ctrl_stress_all_with_rand_reset.79959683116278115414321274337228306521151523517159196594999160620955973438402
      Line 38570, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/3.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        Error-[CNST-STOF] Constraint solver timeout failure
        ../src/lowrisc_dv_sec_cm_0/prim_sparse_fsm_flop_if.sv, 43
          Exceeded cpu time limit during solve.
          Please use the run-time switch +ntb_solver_cpu_limit to increase the cpu
          limit.  The default cpu limit is 1000 seconds per partition.
      

    • 10.lc_ctrl_stress_all_with_rand_reset.79101989068094401892207778754221590429232213011905589948391110552203009437988
      Line 56942, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/10.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        Error-[CNST-STOF] Constraint solver timeout failure
        ../src/lowrisc_dv_sec_cm_0/prim_sparse_fsm_flop_if.sv, 43
          Exceeded cpu time limit during solve.
          Please use the run-time switch +ntb_solver_cpu_limit to increase the cpu
          limit.  The default cpu limit is 1000 seconds per partition.
      

    • ... and 1 more failures.

• UVM_ERROR (cip_base_vseq.sv:551) [lc_ctrl_common_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_state_error fired unexpectedly! has 2 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 2 failures.

    • 33.lc_ctrl_stress_all_with_rand_reset.29792101902977204671910714840962699101091436709540773325083933447277983133084
      Line 15446, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/33.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 57912026830 ps: (cip_base_vseq.sv:551) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
        UVM_INFO @ 57912026830 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 38.lc_ctrl_stress_all_with_rand_reset.45137494750506771255031161384476459423959750537934442096082159090911768836987
      Line 65145, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/38.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 112506872366 ps: (cip_base_vseq.sv:551) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
        UVM_INFO @ 112506872366 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (* [*] vs * [*]) has 1 failures:

  • Test lc_ctrl_stress_all has 1 failures.

    • 34.lc_ctrl_stress_all.18652052907227502245852788324650546832047600026829778665152774722629026231602
      Line 8990, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/34.lc_ctrl_stress_all/latest/run.log

        UVM_ERROR @ 19059244045 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 19059244045 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:749) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 45.lc_ctrl_stress_all_with_rand_reset.64263346024222678105363106359462532734740881657039699368431733978490287755235
      Line 2529, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/45.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1119084707 ps: (cip_base_vseq.sv:749) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
        UVM_INFO @ 1119084707 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

• Latest
• 2024.07.15_09.27.37
• 2024.07.14_08.43.42
• 2024.07.13_08.23.03
• 2024.07.12_09.09.29
• 2024.07.11_10.35.11
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