LC_CTRL/VOLATILE_UNLOCK_DISABLED Simulation Results

Tuesday July 16 2024 23:15:02 UTC

GitHub Revision: aad711e1bc

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 38297581588405771015102977205739484163575733999253050480227719508149669635625

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	11.880s	699.223us	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.180s	20.971us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.210s	66.069us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	2.660s	133.617us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	1.390s	24.625us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	2.050s	30.583us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.210s	66.069us	20	20	100.00
		lc_ctrl_csr_aliasing	1.390s	24.625us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	9.710s	240.818us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	24.270s	833.064us	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	0.970s	13.893us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	5.430s	722.460us	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	35.770s	1.099ms	50	50	100.00
V2	lc_errors	lc_ctrl_errors	19.660s	439.974us	50	50	100.00
V2	security_escalation	lc_ctrl_state_failure	35.770s	1.099ms	50	50	100.00
		lc_ctrl_prog_failure	5.430s	722.460us	50	50	100.00
		lc_ctrl_errors	19.660s	439.974us	50	50	100.00
		lc_ctrl_security_escalation	18.100s	460.658us	50	50	100.00
		lc_ctrl_jtag_state_failure	1.862m	7.092ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	21.230s	922.436us	20	20	100.00
		lc_ctrl_jtag_errors	1.819m	8.177ms	20	20	100.00
V2	jtag_access	lc_ctrl_jtag_smoke	13.210s	4.110ms	20	20	100.00
		lc_ctrl_jtag_state_post_trans	29.840s	6.960ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	21.230s	922.436us	20	20	100.00
		lc_ctrl_jtag_errors	1.819m	8.177ms	20	20	100.00
		lc_ctrl_jtag_access	22.500s	3.875ms	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	35.700s	1.804ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	5.240s	1.554ms	10	10	100.00
		lc_ctrl_jtag_csr_rw	4.360s	186.048us	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	25.120s	9.301ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	17.470s	728.498us	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	1.610s	22.616us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	7.690s	1.696ms	10	10	100.00
		lc_ctrl_jtag_alert_test	2.030s	98.866us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	16.200s	2.289ms	10	10	100.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.270s	19.620us	50	50	100.00
V2	stress_all	lc_ctrl_stress_all	16.408m	30.294ms	50	50	100.00
V2	alert_test	lc_ctrl_alert_test	1.500s	64.238us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	4.000s	143.222us	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	4.000s	143.222us	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.180s	20.971us	5	5	100.00
		lc_ctrl_csr_rw	1.210s	66.069us	20	20	100.00
		lc_ctrl_csr_aliasing	1.390s	24.625us	5	5	100.00
		lc_ctrl_same_csr_outstanding	2.090s	38.125us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.180s	20.971us	5	5	100.00
		lc_ctrl_csr_rw	1.210s	66.069us	20	20	100.00
		lc_ctrl_csr_aliasing	1.390s	24.625us	5	5	100.00
		lc_ctrl_same_csr_outstanding	2.090s	38.125us	20	20	100.00
V2		TOTAL			700	700	100.00
V2S	tl_intg_err	lc_ctrl_sec_cm	41.200s	1.027ms	5	5	100.00
		lc_ctrl_tl_intg_err	5.060s	509.610us	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	5.060s	509.610us	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	24.270s	833.064us	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	35.770s	1.099ms	50	50	100.00
		lc_ctrl_sec_cm	41.200s	1.027ms	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	35.770s	1.099ms	50	50	100.00
		lc_ctrl_sec_cm	41.200s	1.027ms	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	35.770s	1.099ms	50	50	100.00
		lc_ctrl_sec_cm	41.200s	1.027ms	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	35.770s	1.099ms	50	50	100.00
		lc_ctrl_sec_cm	41.200s	1.027ms	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	35.770s	1.099ms	50	50	100.00
		lc_ctrl_sec_cm	41.200s	1.027ms	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	35.770s	1.099ms	50	50	100.00
		lc_ctrl_sec_cm	41.200s	1.027ms	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	35.770s	1.099ms	50	50	100.00
		lc_ctrl_sec_cm	41.200s	1.027ms	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	35.770s	1.099ms	50	50	100.00
		lc_ctrl_sec_cm	41.200s	1.027ms	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	18.100s	460.658us	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	9.710s	240.818us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	29.840s	6.960ms	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	20.910s	540.390us	35	50	70.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	20.910s	540.390us	35	50	70.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	21.220s	978.248us	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	18.260s	539.780us	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	18.260s	539.780us	50	50	100.00
V2S		TOTAL			160	175	91.43
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	1.419h	129.259ms	22	50	44.00
V3		TOTAL			22	50	44.00
		TOTAL			987	1030	95.83

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	27	100.00
V2S	5	5	4	80.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.96	97.92	96.21	93.40	97.62	98.52	98.76	96.29

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:825) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 23 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 23 failures.

    • 1.lc_ctrl_stress_all_with_rand_reset.2068364325270617635186320717531682299871668256492677439207592298054076234891
      Line 10918, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/1.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 3586006820 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 3586006820 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 3.lc_ctrl_stress_all_with_rand_reset.108466276168614353168391123128755313163090040039747501761704749040221024473852
      Line 7371, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/3.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 42330944492 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 42330944492 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 21 more failures.

• UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_sec_mubi_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (* [*] vs * [*]) has 15 failures:

  • Test lc_ctrl_sec_mubi has 15 failures.

    • 0.lc_ctrl_sec_mubi.11927800551621860560115061168542799614218103255930687120253708047120202301398
      Line 502, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/0.lc_ctrl_sec_mubi/latest/run.log

        UVM_ERROR @  19737154 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_sec_mubi_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
        UVM_INFO @  19737154 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 2.lc_ctrl_sec_mubi.25410439243959484991513546383319556044347456481080083384027716590735525914383
      Line 1212, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/2.lc_ctrl_sec_mubi/latest/run.log

        UVM_ERROR @ 274101392 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_sec_mubi_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 274101392 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 13 more failures.

• UVM_ERROR (cip_base_scoreboard.sv:301) scoreboard [scoreboard] alert fatal_prog_error did not trigger max_delay:* has 3 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 3 failures.

    • 19.lc_ctrl_stress_all_with_rand_reset.66651228053157939878849982357180451994269452567955083990768612253838151756613
      Line 6470, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/19.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 26372128848 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 26372128848 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 24.lc_ctrl_stress_all_with_rand_reset.51780846828083755348764718545383443263808385814359996000651349922219650213493
      Line 27921, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/24.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 51646211880 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 51646211880 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 1 more failures.

• UVM_ERROR (cip_base_vseq.sv:551) [lc_ctrl_common_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_state_error fired unexpectedly! has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 29.lc_ctrl_stress_all_with_rand_reset.98262365661815799465910053063088841045959254208536539917946318376359867810882
      Line 13932, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/29.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 30409096234 ps: (cip_base_vseq.sv:551) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
        UVM_INFO @ 30409096234 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Error-[CNST-STOF] Constraint solver timeout failure has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 44.lc_ctrl_stress_all_with_rand_reset.93154169192023813183260905783243601428253075241156525267617497738115612520062
      Line 32240, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/44.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        Error-[CNST-STOF] Constraint solver timeout failure
        ../src/lowrisc_dv_sec_cm_0/prim_sparse_fsm_flop_if.sv, 43
          Exceeded cpu time limit during solve.
          Please use the run-time switch +ntb_solver_cpu_limit to increase the cpu
          limit.  The default cpu limit is 1000 seconds per partition.
      

Past Results

• Latest
• 2024.07.16_09.38.48
• 2024.07.15_09.27.37
• 2024.07.14_08.43.42
• 2024.07.13_08.23.03
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