LC_CTRL/VOLATILE_UNLOCK_DISABLED Simulation Results

Wednesday July 17 2024 23:02:16 UTC

GitHub Revision: 8b2da8db5e

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 31877364624131593519988921539075110140045739991215723614576185349550879231344

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	6.170s	215.888us	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.090s	33.178us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.130s	42.856us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	2.350s	204.998us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	1.470s	154.824us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	2.290s	38.133us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.130s	42.856us	20	20	100.00
		lc_ctrl_csr_aliasing	1.470s	154.824us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	10.890s	239.052us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	18.790s	1.232ms	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	1.020s	13.540us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	4.450s	372.943us	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	35.960s	3.532ms	50	50	100.00
V2	lc_errors	lc_ctrl_errors	21.220s	2.879ms	50	50	100.00
V2	security_escalation	lc_ctrl_state_failure	35.960s	3.532ms	50	50	100.00
		lc_ctrl_prog_failure	4.450s	372.943us	50	50	100.00
		lc_ctrl_errors	21.220s	2.879ms	50	50	100.00
		lc_ctrl_security_escalation	14.970s	393.602us	50	50	100.00
		lc_ctrl_jtag_state_failure	1.389m	8.095ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	15.520s	1.094ms	20	20	100.00
		lc_ctrl_jtag_errors	1.359m	2.846ms	20	20	100.00
V2	jtag_access	lc_ctrl_jtag_smoke	14.330s	3.365ms	20	20	100.00
		lc_ctrl_jtag_state_post_trans	32.650s	3.275ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	15.520s	1.094ms	20	20	100.00
		lc_ctrl_jtag_errors	1.359m	2.846ms	20	20	100.00
		lc_ctrl_jtag_access	21.890s	9.784ms	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	39.470s	5.299ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	4.810s	431.349us	10	10	100.00
		lc_ctrl_jtag_csr_rw	3.440s	507.657us	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	22.470s	7.206ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	23.220s	4.460ms	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	1.600s	42.830us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	7.120s	922.645us	10	10	100.00
		lc_ctrl_jtag_alert_test	3.650s	140.543us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	11.480s	423.514us	10	10	100.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.510s	22.455us	50	50	100.00
V2	stress_all	lc_ctrl_stress_all	9.384m	18.617ms	50	50	100.00
V2	alert_test	lc_ctrl_alert_test	1.300s	24.018us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	4.200s	206.604us	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	4.200s	206.604us	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.090s	33.178us	5	5	100.00
		lc_ctrl_csr_rw	1.130s	42.856us	20	20	100.00
		lc_ctrl_csr_aliasing	1.470s	154.824us	5	5	100.00
		lc_ctrl_same_csr_outstanding	2.030s	100.468us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.090s	33.178us	5	5	100.00
		lc_ctrl_csr_rw	1.130s	42.856us	20	20	100.00
		lc_ctrl_csr_aliasing	1.470s	154.824us	5	5	100.00
		lc_ctrl_same_csr_outstanding	2.030s	100.468us	20	20	100.00
V2		TOTAL			700	700	100.00
V2S	tl_intg_err	lc_ctrl_sec_cm	38.890s	1.247ms	5	5	100.00
		lc_ctrl_tl_intg_err	4.350s	470.437us	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	4.350s	470.437us	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	18.790s	1.232ms	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	35.960s	3.532ms	50	50	100.00
		lc_ctrl_sec_cm	38.890s	1.247ms	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	35.960s	3.532ms	50	50	100.00
		lc_ctrl_sec_cm	38.890s	1.247ms	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	35.960s	3.532ms	50	50	100.00
		lc_ctrl_sec_cm	38.890s	1.247ms	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	35.960s	3.532ms	50	50	100.00
		lc_ctrl_sec_cm	38.890s	1.247ms	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	35.960s	3.532ms	50	50	100.00
		lc_ctrl_sec_cm	38.890s	1.247ms	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	35.960s	3.532ms	50	50	100.00
		lc_ctrl_sec_cm	38.890s	1.247ms	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	35.960s	3.532ms	50	50	100.00
		lc_ctrl_sec_cm	38.890s	1.247ms	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	35.960s	3.532ms	50	50	100.00
		lc_ctrl_sec_cm	38.890s	1.247ms	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	14.970s	393.602us	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	10.890s	239.052us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	32.650s	3.275ms	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	24.760s	4.656ms	43	50	86.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	24.760s	4.656ms	43	50	86.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	26.040s	1.291ms	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	22.360s	2.892ms	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	22.360s	2.892ms	50	50	100.00
V2S		TOTAL			168	175	96.00
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	2.768h	29.733ms	24	50	48.00
V3		TOTAL			24	50	48.00
		TOTAL			997	1030	96.80

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	27	100.00
V2S	5	5	4	80.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.24	97.92	96.03	93.40	100.00	98.52	98.51	96.29

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:839) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 22 failures:
  • Test lc_ctrl_stress_all_with_rand_reset has 22 failures.

    • 0.lc_ctrl_stress_all_with_rand_reset.107265090283715181863861720311907677514531362958611884205395315106282776601310
      Line 26075, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/0.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 104676775744 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 104676775744 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 7.lc_ctrl_stress_all_with_rand_reset.111503021789291999007421565038627623328864048728948723740702764652448972245676
      Line 11049, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/7.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 240722744273 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 240722744273 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 20 more failures.

• UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_sec_mubi_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (* [*] vs * [*]) has 7 failures:
  • Test lc_ctrl_sec_mubi has 7 failures.

    • 0.lc_ctrl_sec_mubi.28086392398693373240528484146131929505992961327017853122266043582203893766135
      Line 2212, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/0.lc_ctrl_sec_mubi/latest/run.log

        UVM_ERROR @ 707444353 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_sec_mubi_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 707444353 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 4.lc_ctrl_sec_mubi.24457268651774714826955514587349096858309537818432496867333272954564901900913
      Line 2308, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/4.lc_ctrl_sec_mubi/latest/run.log

        UVM_ERROR @ 170226347 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_sec_mubi_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 170226347 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 5 more failures.

• UVM_ERROR (cip_base_scoreboard.sv:301) scoreboard [scoreboard] alert fatal_prog_error did not trigger max_delay:* has 3 failures:
  • Test lc_ctrl_stress_all_with_rand_reset has 3 failures.

    • 2.lc_ctrl_stress_all_with_rand_reset.44366983002069662604125010161956007996751297855334076867529951069211150312938
      Line 40413, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/2.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 97170469389 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 97170469389 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 17.lc_ctrl_stress_all_with_rand_reset.53317782068351893054859999621986542501292261590826865437552177429609383887248
      Line 24259, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/17.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 11376663097 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 11376663097 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 1 more failures.

• UVM_ERROR (cip_base_vseq.sv:551) [lc_ctrl_common_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_state_error fired unexpectedly! has 1 failures:
  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 6.lc_ctrl_stress_all_with_rand_reset.18633854165572451350019049965054751949723824990265417294063757992246285667002
      Line 43068, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/6.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 155737719911 ps: (cip_base_vseq.sv:551) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
        UVM_INFO @ 155737719911 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

• Latest
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