LC_CTRL/VOLATILE_UNLOCK_DISABLED Simulation Results

Thursday July 18 2024 23:02:12 UTC

GitHub Revision: 974aaab627

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 46057207235241274571178436692064798722168129065126426307050395083305588858879

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	9.400s	717.087us	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.240s	20.499us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.110s	16.585us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	2.520s	296.001us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	1.210s	31.833us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	2.090s	27.226us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.110s	16.585us	20	20	100.00
		lc_ctrl_csr_aliasing	1.210s	31.833us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	11.540s	2.945ms	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	24.090s	861.634us	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	1.000s	21.278us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	5.310s	249.190us	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	34.200s	978.589us	50	50	100.00
V2	lc_errors	lc_ctrl_errors	23.350s	2.490ms	50	50	100.00
V2	security_escalation	lc_ctrl_state_failure	34.200s	978.589us	50	50	100.00
		lc_ctrl_prog_failure	5.310s	249.190us	50	50	100.00
		lc_ctrl_errors	23.350s	2.490ms	50	50	100.00
		lc_ctrl_security_escalation	16.640s	484.026us	50	50	100.00
		lc_ctrl_jtag_state_failure	1.652m	41.562ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	17.040s	664.385us	20	20	100.00
		lc_ctrl_jtag_errors	1.671m	3.606ms	20	20	100.00
V2	jtag_access	lc_ctrl_jtag_smoke	10.070s	383.284us	20	20	100.00
		lc_ctrl_jtag_state_post_trans	40.460s	2.383ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	17.040s	664.385us	20	20	100.00
		lc_ctrl_jtag_errors	1.671m	3.606ms	20	20	100.00
		lc_ctrl_jtag_access	17.280s	739.871us	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	29.300s	1.888ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	4.210s	163.378us	10	10	100.00
		lc_ctrl_jtag_csr_rw	2.140s	57.453us	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	27.460s	4.417ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	12.960s	2.057ms	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	1.680s	36.003us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	5.260s	705.220us	10	10	100.00
		lc_ctrl_jtag_alert_test	2.530s	332.411us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	25.920s	3.945ms	10	10	100.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.260s	29.674us	50	50	100.00
V2	stress_all	lc_ctrl_stress_all	9.922m	76.060ms	50	50	100.00
V2	alert_test	lc_ctrl_alert_test	1.310s	115.522us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	5.060s	184.021us	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	5.060s	184.021us	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.240s	20.499us	5	5	100.00
		lc_ctrl_csr_rw	1.110s	16.585us	20	20	100.00
		lc_ctrl_csr_aliasing	1.210s	31.833us	5	5	100.00
		lc_ctrl_same_csr_outstanding	2.060s	50.692us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.240s	20.499us	5	5	100.00
		lc_ctrl_csr_rw	1.110s	16.585us	20	20	100.00
		lc_ctrl_csr_aliasing	1.210s	31.833us	5	5	100.00
		lc_ctrl_same_csr_outstanding	2.060s	50.692us	20	20	100.00
V2		TOTAL			700	700	100.00
V2S	tl_intg_err	lc_ctrl_sec_cm	38.040s	967.885us	5	5	100.00
		lc_ctrl_tl_intg_err	3.970s	112.286us	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	3.970s	112.286us	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	24.090s	861.634us	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	34.200s	978.589us	50	50	100.00
		lc_ctrl_sec_cm	38.040s	967.885us	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	34.200s	978.589us	50	50	100.00
		lc_ctrl_sec_cm	38.040s	967.885us	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	34.200s	978.589us	50	50	100.00
		lc_ctrl_sec_cm	38.040s	967.885us	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	34.200s	978.589us	50	50	100.00
		lc_ctrl_sec_cm	38.040s	967.885us	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	34.200s	978.589us	50	50	100.00
		lc_ctrl_sec_cm	38.040s	967.885us	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	34.200s	978.589us	50	50	100.00
		lc_ctrl_sec_cm	38.040s	967.885us	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	34.200s	978.589us	50	50	100.00
		lc_ctrl_sec_cm	38.040s	967.885us	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	34.200s	978.589us	50	50	100.00
		lc_ctrl_sec_cm	38.040s	967.885us	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	16.640s	484.026us	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	11.540s	2.945ms	50	50	100.00
		lc_ctrl_jtag_state_post_trans	40.460s	2.383ms	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	20.270s	2.175ms	38	50	76.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	20.270s	2.175ms	38	50	76.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	25.170s	9.126ms	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	17.310s	2.058ms	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	17.310s	2.058ms	50	50	100.00
V2S		TOTAL			163	175	93.14
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	50.314m	141.547ms	28	50	56.00
V3		TOTAL			28	50	56.00
		TOTAL			996	1030	96.70

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	27	100.00
V2S	5	5	4	80.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.78	97.92	95.56	93.40	97.62	98.52	98.51	95.94

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:839) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 22 failures:
  • Test lc_ctrl_stress_all_with_rand_reset has 22 failures.

    • 0.lc_ctrl_stress_all_with_rand_reset.29049055582531036343384221288270069514977831655459612118361169823741913114208
      Line 30788, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/0.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 45457777240 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 45457777240 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 2.lc_ctrl_stress_all_with_rand_reset.22910423235574598604010754733453417159292137322949836553861040876050934606419
      Line 368, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/2.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 214486040 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10038 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 214486040 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 20 more failures.

• UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_sec_mubi_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (* [*] vs * [*]) has 12 failures:
  • Test lc_ctrl_sec_mubi has 12 failures.

    • 3.lc_ctrl_sec_mubi.107727839689810468383020484024914434690133179546272712470206799525156250741356
      Line 1774, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/3.lc_ctrl_sec_mubi/latest/run.log

        UVM_ERROR @ 175626281 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_sec_mubi_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 175626281 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 6.lc_ctrl_sec_mubi.95789946557736440065345829129774374867103839419320974812512945663526735765488
      Line 1504, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/6.lc_ctrl_sec_mubi/latest/run.log

        UVM_ERROR @ 180754104 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_sec_mubi_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 180754104 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 10 more failures.

Past Results

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