LC_CTRL/VOLATILE_UNLOCK_DISABLED Simulation Results

Friday July 19 2024 23:02:26 UTC

GitHub Revision: e971cd9798

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 26138077499038500271813583950138268511494909685260487774440110801232111361107

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	7.350s	405.493us	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.310s	42.122us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.190s	14.905us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	1.860s	94.746us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	1.490s	29.790us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	2.040s	57.292us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.190s	14.905us	20	20	100.00
		lc_ctrl_csr_aliasing	1.490s	29.790us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	13.010s	90.526us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	21.220s	1.308ms	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	0.980s	19.615us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	5.130s	440.108us	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	36.130s	639.714us	50	50	100.00
V2	lc_errors	lc_ctrl_errors	26.980s	994.598us	50	50	100.00
V2	security_escalation	lc_ctrl_state_failure	36.130s	639.714us	50	50	100.00
		lc_ctrl_prog_failure	5.130s	440.108us	50	50	100.00
		lc_ctrl_errors	26.980s	994.598us	50	50	100.00
		lc_ctrl_security_escalation	14.730s	1.304ms	50	50	100.00
		lc_ctrl_jtag_state_failure	1.413m	4.710ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	29.370s	2.167ms	20	20	100.00
		lc_ctrl_jtag_errors	2.383m	28.426ms	20	20	100.00
V2	jtag_access	lc_ctrl_jtag_smoke	14.180s	1.783ms	20	20	100.00
		lc_ctrl_jtag_state_post_trans	29.980s	2.182ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	29.370s	2.167ms	20	20	100.00
		lc_ctrl_jtag_errors	2.383m	28.426ms	20	20	100.00
		lc_ctrl_jtag_access	26.750s	7.002ms	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	35.810s	1.191ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	4.200s	158.832us	10	10	100.00
		lc_ctrl_jtag_csr_rw	2.720s	164.116us	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	54.970s	40.747ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	14.390s	663.044us	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	1.750s	69.525us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	4.190s	417.701us	10	10	100.00
		lc_ctrl_jtag_alert_test	1.840s	210.267us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	23.080s	1.404ms	10	10	100.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.200s	16.254us	50	50	100.00
V2	stress_all	lc_ctrl_stress_all	13.979m	96.841ms	50	50	100.00
V2	alert_test	lc_ctrl_alert_test	1.420s	277.361us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	4.710s	123.385us	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	4.710s	123.385us	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.310s	42.122us	5	5	100.00
		lc_ctrl_csr_rw	1.190s	14.905us	20	20	100.00
		lc_ctrl_csr_aliasing	1.490s	29.790us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.850s	75.751us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.310s	42.122us	5	5	100.00
		lc_ctrl_csr_rw	1.190s	14.905us	20	20	100.00
		lc_ctrl_csr_aliasing	1.490s	29.790us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.850s	75.751us	20	20	100.00
V2		TOTAL			700	700	100.00
V2S	tl_intg_err	lc_ctrl_sec_cm	35.780s	479.719us	5	5	100.00
		lc_ctrl_tl_intg_err	4.730s	143.510us	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	4.730s	143.510us	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	21.220s	1.308ms	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	36.130s	639.714us	50	50	100.00
		lc_ctrl_sec_cm	35.780s	479.719us	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	36.130s	639.714us	50	50	100.00
		lc_ctrl_sec_cm	35.780s	479.719us	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	36.130s	639.714us	50	50	100.00
		lc_ctrl_sec_cm	35.780s	479.719us	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	36.130s	639.714us	50	50	100.00
		lc_ctrl_sec_cm	35.780s	479.719us	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	36.130s	639.714us	50	50	100.00
		lc_ctrl_sec_cm	35.780s	479.719us	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	36.130s	639.714us	50	50	100.00
		lc_ctrl_sec_cm	35.780s	479.719us	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	36.130s	639.714us	50	50	100.00
		lc_ctrl_sec_cm	35.780s	479.719us	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	36.130s	639.714us	50	50	100.00
		lc_ctrl_sec_cm	35.780s	479.719us	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	14.730s	1.304ms	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	13.010s	90.526us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	29.980s	2.182ms	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	21.800s	753.389us	37	50	74.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	21.800s	753.389us	37	50	74.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	26.230s	6.049ms	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	20.440s	2.282ms	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	20.440s	2.282ms	50	50	100.00
V2S		TOTAL			162	175	92.57
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	34.562m	28.283ms	23	50	46.00
V3		TOTAL			23	50	46.00
		TOTAL			990	1030	96.12

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	27	100.00
V2S	5	5	4	80.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.79	97.92	95.47	93.40	97.62	98.52	98.51	96.11

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:839) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 23 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 23 failures.

    • 2.lc_ctrl_stress_all_with_rand_reset.40687424053413317553346338685672748011967000285255460982668085421934580341463
      Line 4511, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/2.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1747752683 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 1747752683 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 3.lc_ctrl_stress_all_with_rand_reset.111584350633409066235148623254382593752806705275230546828193090801237265764741
      Line 368, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/3.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 225239493 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 225239493 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 21 more failures.

• UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_sec_mubi_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (* [*] vs * [*]) has 13 failures:

  • Test lc_ctrl_sec_mubi has 13 failures.

    • 2.lc_ctrl_sec_mubi.91270615099140970808585310562797076977259633832423110476640200994635838390570
      Line 638, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/2.lc_ctrl_sec_mubi/latest/run.log

        UVM_ERROR @  70036009 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_sec_mubi_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
        UVM_INFO @  70036009 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 4.lc_ctrl_sec_mubi.80199086792451389480788387010417158317973825271493136151717997972475377354723
      Line 1224, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/4.lc_ctrl_sec_mubi/latest/run.log

        UVM_ERROR @ 473220742 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_sec_mubi_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 473220742 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 11 more failures.

• Error-[CNST-STOF] Constraint solver timeout failure has 2 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 2 failures.

    • 13.lc_ctrl_stress_all_with_rand_reset.15808830690742944815568711780910828617252115036030679324407612224095054214497
      Line 32209, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/13.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        Error-[CNST-STOF] Constraint solver timeout failure
        ../src/lowrisc_dv_sec_cm_0/prim_sparse_fsm_flop_if.sv, 43
          Exceeded cpu time limit during solve.
          Please use the run-time switch +ntb_solver_cpu_limit to increase the cpu
          limit.  The default cpu limit is 1000 seconds per partition.
      

    • 43.lc_ctrl_stress_all_with_rand_reset.88534278949719218723429100392049313208181536035410331532034498696111034231191
      Line 48230, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/43.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        Error-[CNST-STOF] Constraint solver timeout failure
        ../src/lowrisc_dv_sec_cm_0/prim_sparse_fsm_flop_if.sv, 43
          Exceeded cpu time limit during solve.
          Please use the run-time switch +ntb_solver_cpu_limit to increase the cpu
          limit.  The default cpu limit is 1000 seconds per partition.
      

• UVM_ERROR (cip_base_vseq.sv:551) [lc_ctrl_regwen_during_op_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_prog_error fired unexpectedly! has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 19.lc_ctrl_stress_all_with_rand_reset.64487132459352579410418737910699547206224418095798234690169161186479245067188
      Line 13536, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/19.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 4817293376 ps: (cip_base_vseq.sv:551) [uvm_test_top.env.virtual_sequencer.lc_ctrl_regwen_during_op_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_prog_error fired unexpectedly!
        UVM_INFO @ 4817293376 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:551) [lc_ctrl_common_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_state_error fired unexpectedly! has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 40.lc_ctrl_stress_all_with_rand_reset.69238564500675477598098056551286576807174205556022149178790844617798662934196
      Line 30033, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/40.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 65848026727 ps: (cip_base_vseq.sv:551) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
        UVM_INFO @ 65848026727 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

• Latest
• 2024.07.19_08.50.29
• 2024.07.18_09.21.58
• 2024.07.17_09.32.17
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