LC_CTRL/VOLATILE_UNLOCK_DISABLED Simulation Results

Saturday July 20 2024 23:02:34 UTC

GitHub Revision: e971cd9798

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 85433431889345478971181747401055702269263498582281270185582621732035232392187

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	11.500s	398.652us	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.140s	33.209us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.200s	19.360us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	3.010s	370.237us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	1.810s	160.961us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	1.840s	31.135us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.200s	19.360us	20	20	100.00
		lc_ctrl_csr_aliasing	1.810s	160.961us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	10.220s	209.321us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	23.010s	5.661ms	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	0.970s	28.205us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	7.090s	725.873us	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	40.200s	737.389us	50	50	100.00
V2	lc_errors	lc_ctrl_errors	24.080s	7.181ms	50	50	100.00
V2	security_escalation	lc_ctrl_state_failure	40.200s	737.389us	50	50	100.00
		lc_ctrl_prog_failure	7.090s	725.873us	50	50	100.00
		lc_ctrl_errors	24.080s	7.181ms	50	50	100.00
		lc_ctrl_security_escalation	17.170s	471.527us	50	50	100.00
		lc_ctrl_jtag_state_failure	1.371m	11.128ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	21.690s	804.767us	20	20	100.00
		lc_ctrl_jtag_errors	1.720m	53.412ms	20	20	100.00
V2	jtag_access	lc_ctrl_jtag_smoke	11.010s	818.970us	20	20	100.00
		lc_ctrl_jtag_state_post_trans	36.850s	2.461ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	21.690s	804.767us	20	20	100.00
		lc_ctrl_jtag_errors	1.720m	53.412ms	20	20	100.00
		lc_ctrl_jtag_access	24.070s	2.083ms	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	29.800s	970.415us	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	4.740s	618.723us	10	10	100.00
		lc_ctrl_jtag_csr_rw	4.080s	641.042us	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	11.480s	423.066us	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	26.710s	4.963ms	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	2.030s	553.023us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	4.370s	521.684us	10	10	100.00
		lc_ctrl_jtag_alert_test	2.290s	861.200us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	14.860s	1.097ms	10	10	100.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.170s	20.105us	50	50	100.00
V2	stress_all	lc_ctrl_stress_all	10.779m	87.836ms	50	50	100.00
V2	alert_test	lc_ctrl_alert_test	1.450s	29.466us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	4.450s	721.646us	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	4.450s	721.646us	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.140s	33.209us	5	5	100.00
		lc_ctrl_csr_rw	1.200s	19.360us	20	20	100.00
		lc_ctrl_csr_aliasing	1.810s	160.961us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.910s	44.124us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.140s	33.209us	5	5	100.00
		lc_ctrl_csr_rw	1.200s	19.360us	20	20	100.00
		lc_ctrl_csr_aliasing	1.810s	160.961us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.910s	44.124us	20	20	100.00
V2		TOTAL			700	700	100.00
V2S	tl_intg_err	lc_ctrl_sec_cm	39.600s	1.150ms	5	5	100.00
		lc_ctrl_tl_intg_err	4.420s	164.410us	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	4.420s	164.410us	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	23.010s	5.661ms	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	40.200s	737.389us	50	50	100.00
		lc_ctrl_sec_cm	39.600s	1.150ms	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	40.200s	737.389us	50	50	100.00
		lc_ctrl_sec_cm	39.600s	1.150ms	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	40.200s	737.389us	50	50	100.00
		lc_ctrl_sec_cm	39.600s	1.150ms	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	40.200s	737.389us	50	50	100.00
		lc_ctrl_sec_cm	39.600s	1.150ms	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	40.200s	737.389us	50	50	100.00
		lc_ctrl_sec_cm	39.600s	1.150ms	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	40.200s	737.389us	50	50	100.00
		lc_ctrl_sec_cm	39.600s	1.150ms	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	40.200s	737.389us	50	50	100.00
		lc_ctrl_sec_cm	39.600s	1.150ms	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	40.200s	737.389us	50	50	100.00
		lc_ctrl_sec_cm	39.600s	1.150ms	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	17.170s	471.527us	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	10.220s	209.321us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	36.850s	2.461ms	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	28.590s	10.599ms	45	50	90.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	28.590s	10.599ms	45	50	90.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	24.310s	1.044ms	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	19.530s	6.414ms	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	19.530s	6.414ms	50	50	100.00
V2S		TOTAL			170	175	97.14
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	1.118h	34.392ms	26	50	52.00
V3		TOTAL			26	50	52.00
		TOTAL			1001	1030	97.18

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	27	100.00
V2S	5	5	4	80.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.83	97.92	95.75	93.40	97.62	98.52	98.51	96.11

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:839) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 18 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 18 failures.

    • 4.lc_ctrl_stress_all_with_rand_reset.28024295121948196920933673685647904668784778361397765938778205006475900524996
      Line 32229, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/4.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 42583548770 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 42583548770 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 7.lc_ctrl_stress_all_with_rand_reset.73465370700587096150478614850171233607662495373245288064564331339675698604346
      Line 23146, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/7.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 26075097411 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 26075097411 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 16 more failures.

• UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_sec_mubi_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (* [*] vs * [*]) has 5 failures:

  • Test lc_ctrl_sec_mubi has 5 failures.

    • 4.lc_ctrl_sec_mubi.63948262816964143063556123347212679234435366291833833543811859877470049517968
      Line 2948, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/4.lc_ctrl_sec_mubi/latest/run.log

        UVM_ERROR @ 258411580 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_sec_mubi_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 258411580 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 8.lc_ctrl_sec_mubi.94842161006271010008537004129879570119222470370549417542584750931132154522209
      Line 552, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/8.lc_ctrl_sec_mubi/latest/run.log

        UVM_ERROR @  20968333 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_sec_mubi_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
        UVM_INFO @  20968333 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 3 more failures.

• UVM_ERROR (cip_base_scoreboard.sv:301) scoreboard [scoreboard] alert fatal_prog_error did not trigger max_delay:* has 2 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 2 failures.

    • 16.lc_ctrl_stress_all_with_rand_reset.2613092620796466041647949218601596920695108465007122612526591155384397194806
      Line 27019, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/16.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 38034657616 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 38034657616 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 38.lc_ctrl_stress_all_with_rand_reset.50759679043965843772386255456441451614292942226381711069469493700480324720425
      Line 18300, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/38.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 37319070988 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 37319070988 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (* [*] vs * [*]) has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 1.lc_ctrl_stress_all_with_rand_reset.82924162847493506904598133724003885938680473457975577722588836933116046020608
      Line 10642, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/1.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 2062469562 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 2062469562 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Error-[CNST-STOF] Constraint solver timeout failure has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 13.lc_ctrl_stress_all_with_rand_reset.30506553354769621573922050387389855355556073202444686477517189819906413418209
      Line 25380, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/13.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        Error-[CNST-STOF] Constraint solver timeout failure
        ../src/lowrisc_dv_sec_cm_0/prim_sparse_fsm_flop_if.sv, 43
          Exceeded cpu time limit during solve.
          Please use the run-time switch +ntb_solver_cpu_limit to increase the cpu
          limit.  The default cpu limit is 1000 seconds per partition.
      

• UVM_ERROR (lc_ctrl_scoreboard.sv:238) [scoreboard] Check failed cfg.lc_ctrl_vif.lc_dft_en_o == exp_o.lc_dft_en_o (* [*] vs * [*]) Called from line: *, LC_St DecLcStTestUnlocked* has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 19.lc_ctrl_stress_all_with_rand_reset.47306915128114670718931836012072947148733834775281794994958483426216245847308
      Line 42172, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/19.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 75604730972 ps: (lc_ctrl_scoreboard.sv:238) [uvm_test_top.env.scoreboard] Check failed cfg.lc_ctrl_vif.lc_dft_en_o == exp_o.lc_dft_en_o (5 [0x5] vs 10 [0xa]) Called from line: 100, LC_St DecLcStTestUnlocked4
        UVM_INFO @ 75604730972 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:551) [lc_ctrl_common_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_state_error fired unexpectedly! has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 39.lc_ctrl_stress_all_with_rand_reset.82213760143988756068768315724624569881209079248105751583933899426260480257988
      Line 24254, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/39.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 10895233720 ps: (cip_base_vseq.sv:551) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
        UVM_INFO @ 10895233720 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

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