LC_CTRL/VOLATILE_UNLOCK_DISABLED Simulation Results

Sunday July 21 2024 23:02:06 UTC

GitHub Revision: `e971cd9798`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 60538554475599760039478308558126864941531727393021608909386829062452482962039

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	6.270s	455.788us	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.290s	134.022us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.160s	18.326us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	2.530s	526.144us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	1.330s	42.010us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	1.640s	48.765us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.160s	18.326us	20	20	100.00
		lc_ctrl_csr_aliasing	1.330s	42.010us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	10.130s	86.103us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	15.100s	459.392us	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	0.980s	13.464us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	5.730s	141.859us	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	34.290s	302.665us	50	50	100.00
V2	lc_errors	lc_ctrl_errors	28.910s	3.160ms	50	50	100.00
V2	security_escalation	lc_ctrl_state_failure	34.290s	302.665us	50	50	100.00
		lc_ctrl_prog_failure	5.730s	141.859us	50	50	100.00
		lc_ctrl_errors	28.910s	3.160ms	50	50	100.00
		lc_ctrl_security_escalation	14.950s	2.091ms	50	50	100.00
		lc_ctrl_jtag_state_failure	2.473m	9.513ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	17.440s	597.322us	20	20	100.00
		lc_ctrl_jtag_errors	1.404m	11.642ms	20	20	100.00
V2	jtag_access	lc_ctrl_jtag_smoke	7.400s	1.739ms	20	20	100.00
		lc_ctrl_jtag_state_post_trans	29.830s	3.642ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	17.440s	597.322us	20	20	100.00
		lc_ctrl_jtag_errors	1.404m	11.642ms	20	20	100.00
		lc_ctrl_jtag_access	13.970s	2.147ms	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	25.510s	914.602us	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	4.770s	782.210us	10	10	100.00
		lc_ctrl_jtag_csr_rw	3.890s	532.681us	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	21.800s	4.041ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	17.090s	2.993ms	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	1.550s	185.371us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	4.650s	154.143us	10	10	100.00
		lc_ctrl_jtag_alert_test	2.520s	110.718us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	19.910s	1.536ms	10	10	100.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.140s	63.407us	50	50	100.00
V2	stress_all	lc_ctrl_stress_all	10.614m	21.045ms	48	50	96.00
V2	alert_test	lc_ctrl_alert_test	1.600s	179.470us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	4.330s	412.231us	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	4.330s	412.231us	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.290s	134.022us	5	5	100.00
		lc_ctrl_csr_rw	1.160s	18.326us	20	20	100.00
		lc_ctrl_csr_aliasing	1.330s	42.010us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.840s	86.263us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.290s	134.022us	5	5	100.00
		lc_ctrl_csr_rw	1.160s	18.326us	20	20	100.00
		lc_ctrl_csr_aliasing	1.330s	42.010us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.840s	86.263us	20	20	100.00
V2		TOTAL			698	700	99.71
V2S	tl_intg_err	lc_ctrl_sec_cm	43.940s	250.356us	5	5	100.00
		lc_ctrl_tl_intg_err	4.530s	438.326us	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	4.530s	438.326us	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	15.100s	459.392us	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	34.290s	302.665us	50	50	100.00
		lc_ctrl_sec_cm	43.940s	250.356us	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	34.290s	302.665us	50	50	100.00
		lc_ctrl_sec_cm	43.940s	250.356us	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	34.290s	302.665us	50	50	100.00
		lc_ctrl_sec_cm	43.940s	250.356us	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	34.290s	302.665us	50	50	100.00
		lc_ctrl_sec_cm	43.940s	250.356us	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	34.290s	302.665us	50	50	100.00
		lc_ctrl_sec_cm	43.940s	250.356us	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	34.290s	302.665us	50	50	100.00
		lc_ctrl_sec_cm	43.940s	250.356us	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	34.290s	302.665us	50	50	100.00
		lc_ctrl_sec_cm	43.940s	250.356us	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	34.290s	302.665us	50	50	100.00
		lc_ctrl_sec_cm	43.940s	250.356us	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	14.950s	2.091ms	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	10.130s	86.103us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	29.830s	3.642ms	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	21.260s	3.066ms	42	50	84.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	21.260s	3.066ms	42	50	84.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	26.140s	3.138ms	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	25.620s	11.944ms	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	25.620s	11.944ms	50	50	100.00
V2S		TOTAL			167	175	95.43
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	46.762m	125.739ms	22	50	44.00
V3		TOTAL			22	50	44.00
		TOTAL			992	1030	96.31

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	26	96.30
V2S	5	5	4	80.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.81	97.92	95.56	93.40	97.62	98.52	98.51	96.11

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:839) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 19 failures:
- Test lc_ctrl_stress_all_with_rand_reset has 19 failures.
  - 0.lc_ctrl_stress_all_with_rand_reset.28290254336212713403580269551951844159659817193345097227098158769156603325439
    Line 14471, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/0.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 36160667298 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 36160667298 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.lc_ctrl_stress_all_with_rand_reset.104625353463303245803646358927265891333106735338351393630093807729511467304715
    Line 25532, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/1.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 20436100139 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 20436100139 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 17 more failures.
UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_sec_mubi_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (* [*] vs * [*]) has 8 failures:
- Test lc_ctrl_sec_mubi has 8 failures.
  - 3.lc_ctrl_sec_mubi.676448416846253289683800010003232388404223080520469127762444825245576886734
    Line 1766, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/3.lc_ctrl_sec_mubi/latest/run.log
```
  UVM_ERROR @ 2997203439 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_sec_mubi_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 2997203439 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 5.lc_ctrl_sec_mubi.41468915997910308194572669693633636939218106558697177825711893966466652308917
    Line 2716, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/5.lc_ctrl_sec_mubi/latest/run.log
```
  UVM_ERROR @ 781425070 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_sec_mubi_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 781425070 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 6 more failures.
UVM_ERROR (cip_base_vseq.sv:551) [lc_ctrl_common_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_state_error fired unexpectedly! has 3 failures:
- Test lc_ctrl_stress_all_with_rand_reset has 3 failures.
  - 18.lc_ctrl_stress_all_with_rand_reset.90764802405487084563326688145123291143737107468480863431225311140723729345543
    Line 23467, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/18.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 145732229031 ps: (cip_base_vseq.sv:551) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
  UVM_INFO @ 145732229031 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 31.lc_ctrl_stress_all_with_rand_reset.10405202860603539227263043357485888876199008836845251136159087939381976821289
    Line 35165, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/31.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 35162287511 ps: (cip_base_vseq.sv:551) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
  UVM_INFO @ 35162287511 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_ERROR (cip_base_scoreboard.sv:301) scoreboard [scoreboard] alert fatal_prog_error did not trigger max_delay:* has 2 failures:
- Test lc_ctrl_stress_all_with_rand_reset has 1 failures.
  - 14.lc_ctrl_stress_all_with_rand_reset.72608888254426103682011770466678375191756019554889876275320565439695425341208
    Line 21488, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/14.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 39034613624 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
  UVM_INFO @ 39034613624 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test lc_ctrl_stress_all has 1 failures.
  - 46.lc_ctrl_stress_all.67432916882262699853200266454704185844949433235297465377155920693313895925632
    Line 8476, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/46.lc_ctrl_stress_all/latest/run.log
```
  UVM_ERROR @ 11339375395 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
  UVM_INFO @ 11339375395 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Error-[CNST-STOF] Constraint solver timeout failure has 1 failures:
- Test lc_ctrl_stress_all_with_rand_reset has 1 failures.
  - 6.lc_ctrl_stress_all_with_rand_reset.96074233177966805480656819378159694251058501748322325028871353406198925488984
    Line 31107, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/6.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Error-[CNST-STOF] Constraint solver timeout failure
  ../src/lowrisc_dv_sec_cm_0/prim_sparse_fsm_flop_if.sv, 43
    Exceeded cpu time limit during solve.
    Please use the run-time switch +ntb_solver_cpu_limit to increase the cpu
    limit.  The default cpu limit is 1000 seconds per partition.
```
UVM_ERROR (lc_ctrl_errors_vseq.sv:769) [lc_ctrl_lc_errors_vseq] Check failed otp_error_act == otp_error_exp (* [*] vs * [*]) has 1 failures:
- Test lc_ctrl_stress_all_with_rand_reset has 1 failures.
  - 15.lc_ctrl_stress_all_with_rand_reset.9097679372243896440750429831507772684755239711293078359671795437681904704094
    Line 16532, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/15.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 4020356314 ps: (lc_ctrl_errors_vseq.sv:769) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed otp_error_act == otp_error_exp (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 4020356314 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Job lc_ctrl_volatile_unlock_disabled-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:
- Test lc_ctrl_stress_all_with_rand_reset has 1 failures.
  - 27.lc_ctrl_stress_all_with_rand_reset.46701878133404613602110774654117790353008884650982158112634822045037072204882
    Log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/27.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:aa1edcd3-5926-424c-aeb4-a83aa2412509
```
UVM_ERROR (lc_ctrl_scoreboard.sv:238) [scoreboard] Check failed cfg.lc_ctrl_vif.lc_dft_en_o == exp_o.lc_dft_en_o (* [*] vs * [*]) Called from line: *, LC_St DecLcStTestUnlocked* has 1 failures:
- Test lc_ctrl_stress_all_with_rand_reset has 1 failures.
  - 34.lc_ctrl_stress_all_with_rand_reset.18266866015765584140420930590724976479177325084838958005498574847902883209058
    Line 21557, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/34.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 12928334536 ps: (lc_ctrl_scoreboard.sv:238) [uvm_test_top.env.scoreboard] Check failed cfg.lc_ctrl_vif.lc_dft_en_o == exp_o.lc_dft_en_o (5 [0x5] vs 10 [0xa]) Called from line: 100, LC_St DecLcStTestUnlocked0
  UVM_INFO @ 12928334536 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (* [*] vs * [*]) has 1 failures:
- Test lc_ctrl_stress_all has 1 failures.
  - 44.lc_ctrl_stress_all.105604633320029924015041584207341331919357414691839210964195524623441226288501
    Line 3502, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/44.lc_ctrl_stress_all/latest/run.log
```
  UVM_ERROR @ 1359336215 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 1359336215 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (lc_ctrl_scoreboard.sv:240) [scoreboard] Check failed cfg.lc_ctrl_vif.lc_hw_debug_en_o == exp_o.lc_hw_debug_en_o (* [*] vs * [*]) Called from line: *, LC_St DecLcStDev has 1 failures:
- Test lc_ctrl_stress_all_with_rand_reset has 1 failures.
  - 44.lc_ctrl_stress_all_with_rand_reset.12519402517769541163831358067471528219520873064867193836936707624592728775268
    Line 25357, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/44.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 14878302533 ps: (lc_ctrl_scoreboard.sv:240) [uvm_test_top.env.scoreboard] Check failed cfg.lc_ctrl_vif.lc_hw_debug_en_o == exp_o.lc_hw_debug_en_o (5 [0x5] vs 10 [0xa]) Called from line: 100, LC_St DecLcStDev
  UVM_INFO @ 14878302533 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

LC_CTRL/VOLATILE_UNLOCK_DISABLED Simulation Results

Sunday July 21 2024 23:02:06 UTC

GitHub Revision: e971cd9798

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 60538554475599760039478308558126864941531727393021608909386829062452482962039

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `e971cd9798`