LC_CTRL/VOLATILE_UNLOCK_DISABLED Simulation Results

Monday July 22 2024 23:02:17 UTC

GitHub Revision: 3e0219a2c5

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 78193674045195286552709223969981662100934453993551616519215297815848091296886

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	8.130s	169.076us	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.320s	69.747us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.090s	16.155us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	2.520s	410.470us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	1.370s	35.285us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	2.000s	156.005us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.090s	16.155us	20	20	100.00
		lc_ctrl_csr_aliasing	1.370s	35.285us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	10.470s	93.413us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	22.800s	665.943us	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	0.960s	12.899us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	4.600s	414.132us	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	37.090s	681.042us	50	50	100.00
V2	lc_errors	lc_ctrl_errors	20.930s	724.972us	50	50	100.00
V2	security_escalation	lc_ctrl_state_failure	37.090s	681.042us	50	50	100.00
		lc_ctrl_prog_failure	4.600s	414.132us	50	50	100.00
		lc_ctrl_errors	20.930s	724.972us	50	50	100.00
		lc_ctrl_security_escalation	20.790s	549.057us	50	50	100.00
		lc_ctrl_jtag_state_failure	1.298m	7.278ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	21.790s	848.074us	20	20	100.00
		lc_ctrl_jtag_errors	2.350m	5.276ms	19	20	95.00
V2	jtag_access	lc_ctrl_jtag_smoke	13.760s	5.415ms	20	20	100.00
		lc_ctrl_jtag_state_post_trans	31.550s	4.447ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	21.790s	848.074us	20	20	100.00
		lc_ctrl_jtag_errors	2.350m	5.276ms	19	20	95.00
		lc_ctrl_jtag_access	15.030s	2.602ms	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	27.420s	6.729ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	6.350s	746.110us	10	10	100.00
		lc_ctrl_jtag_csr_rw	2.440s	66.550us	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	24.740s	2.367ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	12.190s	2.276ms	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	1.580s	22.377us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	3.880s	1.338ms	10	10	100.00
		lc_ctrl_jtag_alert_test	3.050s	420.287us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	18.760s	7.820ms	10	10	100.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.180s	106.169us	50	50	100.00
V2	stress_all	lc_ctrl_stress_all	11.901m	23.844ms	49	50	98.00
V2	alert_test	lc_ctrl_alert_test	1.480s	26.493us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	4.640s	1.166ms	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	4.640s	1.166ms	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.320s	69.747us	5	5	100.00
		lc_ctrl_csr_rw	1.090s	16.155us	20	20	100.00
		lc_ctrl_csr_aliasing	1.370s	35.285us	5	5	100.00
		lc_ctrl_same_csr_outstanding	2.020s	234.995us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.320s	69.747us	5	5	100.00
		lc_ctrl_csr_rw	1.090s	16.155us	20	20	100.00
		lc_ctrl_csr_aliasing	1.370s	35.285us	5	5	100.00
		lc_ctrl_same_csr_outstanding	2.020s	234.995us	20	20	100.00
V2		TOTAL			698	700	99.71
V2S	tl_intg_err	lc_ctrl_sec_cm	43.120s	3.882ms	5	5	100.00
		lc_ctrl_tl_intg_err	4.460s	120.048us	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	4.460s	120.048us	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	22.800s	665.943us	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	37.090s	681.042us	50	50	100.00
		lc_ctrl_sec_cm	43.120s	3.882ms	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	37.090s	681.042us	50	50	100.00
		lc_ctrl_sec_cm	43.120s	3.882ms	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	37.090s	681.042us	50	50	100.00
		lc_ctrl_sec_cm	43.120s	3.882ms	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	37.090s	681.042us	50	50	100.00
		lc_ctrl_sec_cm	43.120s	3.882ms	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	37.090s	681.042us	50	50	100.00
		lc_ctrl_sec_cm	43.120s	3.882ms	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	37.090s	681.042us	50	50	100.00
		lc_ctrl_sec_cm	43.120s	3.882ms	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	37.090s	681.042us	50	50	100.00
		lc_ctrl_sec_cm	43.120s	3.882ms	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	37.090s	681.042us	50	50	100.00
		lc_ctrl_sec_cm	43.120s	3.882ms	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	20.790s	549.057us	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	10.470s	93.413us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	31.550s	4.447ms	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	29.940s	2.824ms	38	50	76.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	29.940s	2.824ms	38	50	76.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	26.120s	4.633ms	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	18.160s	546.008us	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	18.160s	546.008us	50	50	100.00
V2S		TOTAL			163	175	93.14
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	1.117h	43.571ms	32	50	64.00
V3		TOTAL			32	50	64.00
		TOTAL			998	1030	96.89

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	25	92.59
V2S	5	5	4	80.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.17	97.92	95.75	93.40	100.00	98.52	98.51	96.11

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:839) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 15 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 15 failures.

    • 1.lc_ctrl_stress_all_with_rand_reset.1156704641683768314806251053982454365964365886701561714989800870278534734804
      Line 14608, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/1.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 25727925643 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 25727925643 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 3.lc_ctrl_stress_all_with_rand_reset.88026393161957787366015219505525551248004366151082999443042188914443186801930
      Line 42544, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/3.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 121162849265 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 121162849265 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 13 more failures.

• UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_sec_mubi_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (* [*] vs * [*]) has 12 failures:

  • Test lc_ctrl_sec_mubi has 12 failures.

    • 1.lc_ctrl_sec_mubi.69908675279670369530555246319397520124976890744299527528705792993478259701538
      Line 638, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/1.lc_ctrl_sec_mubi/latest/run.log

        UVM_ERROR @  94202137 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_sec_mubi_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
        UVM_INFO @  94202137 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 4.lc_ctrl_sec_mubi.69613302115702803846162437656006474150438501692077689503206135124825917018391
      Line 2764, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/4.lc_ctrl_sec_mubi/latest/run.log

        UVM_ERROR @ 501518110 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_sec_mubi_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 501518110 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 10 more failures.

• UVM_ERROR (cip_base_scoreboard.sv:301) scoreboard [scoreboard] alert fatal_prog_error did not trigger max_delay:* has 3 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 2 failures.

    • 20.lc_ctrl_stress_all_with_rand_reset.48600491256443792184968549101713711006476359492386941205974851720978621583724
      Line 10974, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/20.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 36850250084 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 36850250084 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 39.lc_ctrl_stress_all_with_rand_reset.39615579396977752086315225623209267179886109497052255211614552472244174986245
      Line 11982, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/39.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 6024640609 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 6024640609 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test lc_ctrl_stress_all has 1 failures.

    • 45.lc_ctrl_stress_all.78189311057761561954169278318175908089499077522310963807099338933824931992554
      Line 11796, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/45.lc_ctrl_stress_all/latest/run.log

        UVM_ERROR @ 103739180335 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 103739180335 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (* [*] vs * [*]) has 1 failures:

  • Test lc_ctrl_jtag_errors has 1 failures.

    • 1.lc_ctrl_jtag_errors.8658227611736629044180253830009526450803423335457476536209450206563004926646
      Line 1608, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/1.lc_ctrl_jtag_errors/latest/run.log

        UVM_ERROR @ 1894357410 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 1894357410 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:551) [lc_ctrl_regwen_during_op_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_prog_error fired unexpectedly! has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 45.lc_ctrl_stress_all_with_rand_reset.105620158700923323139566902101488319205747453617130663075325123512148774953776
      Line 26807, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/45.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 30522179056 ps: (cip_base_vseq.sv:551) [uvm_test_top.env.virtual_sequencer.lc_ctrl_regwen_during_op_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_prog_error fired unexpectedly!
        UVM_INFO @ 30522179056 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

• Latest
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• 2024.07.21_08.25.14
• 2024.07.20_09.48.22
• 2024.07.19_08.50.29
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