LC_CTRL/VOLATILE_UNLOCK_DISABLED Simulation Results

Tuesday July 23 2024 23:02:17 UTC

GitHub Revision: 0bfa990ddc

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 18885947517810151702135064218189465175127531856323617115052940021793720055953

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	11.680s	978.390us	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.090s	38.480us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.140s	18.595us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	1.360s	51.639us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	1.930s	41.898us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	2.070s	31.626us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.140s	18.595us	20	20	100.00
		lc_ctrl_csr_aliasing	1.930s	41.898us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	10.110s	174.957us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	19.580s	659.265us	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	1.020s	13.014us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	4.700s	98.127us	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	35.200s	289.127us	50	50	100.00
V2	lc_errors	lc_ctrl_errors	25.450s	692.218us	50	50	100.00
V2	security_escalation	lc_ctrl_state_failure	35.200s	289.127us	50	50	100.00
		lc_ctrl_prog_failure	4.700s	98.127us	50	50	100.00
		lc_ctrl_errors	25.450s	692.218us	50	50	100.00
		lc_ctrl_security_escalation	15.750s	469.972us	50	50	100.00
		lc_ctrl_jtag_state_failure	1.774m	2.922ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	15.440s	505.538us	20	20	100.00
		lc_ctrl_jtag_errors	1.154m	4.521ms	20	20	100.00
V2	jtag_access	lc_ctrl_jtag_smoke	13.680s	2.199ms	20	20	100.00
		lc_ctrl_jtag_state_post_trans	29.060s	857.679us	20	20	100.00
		lc_ctrl_jtag_prog_failure	15.440s	505.538us	20	20	100.00
		lc_ctrl_jtag_errors	1.154m	4.521ms	20	20	100.00
		lc_ctrl_jtag_access	26.590s	4.353ms	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	37.530s	5.127ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	5.510s	212.413us	10	10	100.00
		lc_ctrl_jtag_csr_rw	2.750s	84.387us	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	46.450s	4.243ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	28.620s	2.713ms	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	1.890s	144.051us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	4.380s	634.433us	10	10	100.00
		lc_ctrl_jtag_alert_test	2.530s	190.862us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	30.860s	2.750ms	10	10	100.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.150s	16.942us	48	50	96.00
V2	stress_all	lc_ctrl_stress_all	11.543m	394.462ms	50	50	100.00
V2	alert_test	lc_ctrl_alert_test	1.620s	285.322us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	6.300s	820.183us	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	6.300s	820.183us	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.090s	38.480us	5	5	100.00
		lc_ctrl_csr_rw	1.140s	18.595us	20	20	100.00
		lc_ctrl_csr_aliasing	1.930s	41.898us	5	5	100.00
		lc_ctrl_same_csr_outstanding	2.030s	90.252us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.090s	38.480us	5	5	100.00
		lc_ctrl_csr_rw	1.140s	18.595us	20	20	100.00
		lc_ctrl_csr_aliasing	1.930s	41.898us	5	5	100.00
		lc_ctrl_same_csr_outstanding	2.030s	90.252us	20	20	100.00
V2		TOTAL			698	700	99.71
V2S	tl_intg_err	lc_ctrl_sec_cm	39.440s	939.280us	5	5	100.00
		lc_ctrl_tl_intg_err	4.300s	482.363us	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	4.300s	482.363us	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	19.580s	659.265us	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	35.200s	289.127us	50	50	100.00
		lc_ctrl_sec_cm	39.440s	939.280us	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	35.200s	289.127us	50	50	100.00
		lc_ctrl_sec_cm	39.440s	939.280us	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	35.200s	289.127us	50	50	100.00
		lc_ctrl_sec_cm	39.440s	939.280us	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	35.200s	289.127us	50	50	100.00
		lc_ctrl_sec_cm	39.440s	939.280us	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	35.200s	289.127us	50	50	100.00
		lc_ctrl_sec_cm	39.440s	939.280us	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	35.200s	289.127us	50	50	100.00
		lc_ctrl_sec_cm	39.440s	939.280us	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	35.200s	289.127us	50	50	100.00
		lc_ctrl_sec_cm	39.440s	939.280us	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	35.200s	289.127us	50	50	100.00
		lc_ctrl_sec_cm	39.440s	939.280us	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	15.750s	469.972us	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	10.110s	174.957us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	29.060s	857.679us	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	18.590s	450.141us	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	18.590s	450.141us	50	50	100.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	26.950s	5.083ms	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	17.840s	622.135us	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	17.840s	622.135us	50	50	100.00
V2S		TOTAL			175	175	100.00
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	40.741m	86.577ms	32	50	64.00
V3		TOTAL			32	50	64.00
		TOTAL			1010	1030	98.06

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	26	96.30
V2S	5	5	5	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.27	97.92	96.21	93.40	100.00	98.52	98.76	96.11

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:839) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 14 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 14 failures.

    • 0.lc_ctrl_stress_all_with_rand_reset.23117100540329838387827047504887828929659073692607638910731679713655050011085
      Line 341, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/0.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 5226736847 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 5226736847 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 6.lc_ctrl_stress_all_with_rand_reset.37510014835105776783791783839955875077586422581468182299884108251033666947113
      Line 19352, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/6.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 18556591334 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 18556591334 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 12 more failures.

• UVM_ERROR (cip_base_scoreboard.sv:301) scoreboard [scoreboard] alert fatal_prog_error did not trigger max_delay:* has 2 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 2 failures.

    • 5.lc_ctrl_stress_all_with_rand_reset.115027885699135986700165858956411384219327241333931911501947692837774527851331
      Line 7198, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/5.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 75369959569 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 75369959569 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 33.lc_ctrl_stress_all_with_rand_reset.52975885495205386254431267447693678811475823794336958302298793236932974346426
      Line 8262, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/33.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 4899726215 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 4899726215 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (csr_utils_pkg.sv:594) [csr_utils::csr_spinwait] timeout lc_ctrl_reg_block.status.token_error (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=1) has 2 failures:

  • Test lc_ctrl_volatile_unlock_smoke has 2 failures.

    • 19.lc_ctrl_volatile_unlock_smoke.67957558816916021446857160963966910766776569218632097466994660293060974944667
      Line 322, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/19.lc_ctrl_volatile_unlock_smoke/latest/run.log

        UVM_FATAL @ 131724872 ps: (csr_utils_pkg.sv:594) [csr_utils::csr_spinwait] timeout lc_ctrl_reg_block.status.token_error (addr=0xeb85f804, Comparison=CompareOpEq, exp_data=0x1, call_count=1)
        UVM_INFO @ 131724872 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 48.lc_ctrl_volatile_unlock_smoke.3791171705244172306846987889658336813333821466095733949057484406092175919156
      Line 322, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/48.lc_ctrl_volatile_unlock_smoke/latest/run.log

        UVM_FATAL @ 122810420 ps: (csr_utils_pkg.sv:594) [csr_utils::csr_spinwait] timeout lc_ctrl_reg_block.status.token_error (addr=0x232bd604, Comparison=CompareOpEq, exp_data=0x1, call_count=1)
        UVM_INFO @ 122810420 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Error-[CNST-STOF] Constraint solver timeout failure has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 16.lc_ctrl_stress_all_with_rand_reset.29425280352842540835778101858503613955424132962488172555191190215812700229735
      Line 41097, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/16.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        Error-[CNST-STOF] Constraint solver timeout failure
        ../src/lowrisc_dv_sec_cm_0/prim_sparse_fsm_flop_if.sv, 43
          Exceeded cpu time limit during solve.
          Please use the run-time switch +ntb_solver_cpu_limit to increase the cpu
          limit.  The default cpu limit is 1000 seconds per partition.
      

• UVM_ERROR (lc_ctrl_scoreboard.sv:243) [scoreboard] Check failed cfg.lc_ctrl_vif.lc_escalate_en_o == exp_o.lc_escalate_en_o (* [*] vs * [*]) Called from line: *, LC_St DecLcStTestLocked* has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 21.lc_ctrl_stress_all_with_rand_reset.18915479852100376441388855846171396653784909101759321699902139160064121768222
      Line 964, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/21.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1939713644 ps: (lc_ctrl_scoreboard.sv:243) [uvm_test_top.env.scoreboard] Check failed cfg.lc_ctrl_vif.lc_escalate_en_o == exp_o.lc_escalate_en_o (10 [0xa] vs 5 [0x5]) Called from line: 100, LC_St DecLcStTestLocked3
        UVM_INFO @ 1939713644 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

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