LC_CTRL/VOLATILE_UNLOCK_DISABLED Simulation Results

Wednesday July 24 2024 23:04:46 UTC

GitHub Revision: e439226b6c

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 80778109121175195808319778278610424989650974127729484509360263424111433728567

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	7.770s	295.580us	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.250s	34.148us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.150s	18.044us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	1.940s	47.206us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	1.340s	23.592us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	1.850s	21.961us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.150s	18.044us	20	20	100.00
		lc_ctrl_csr_aliasing	1.340s	23.592us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	11.250s	236.137us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	22.410s	335.266us	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	1.020s	14.857us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	4.200s	166.045us	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	35.680s	1.478ms	50	50	100.00
V2	lc_errors	lc_ctrl_errors	26.930s	621.111us	50	50	100.00
V2	security_escalation	lc_ctrl_state_failure	35.680s	1.478ms	50	50	100.00
		lc_ctrl_prog_failure	4.200s	166.045us	50	50	100.00
		lc_ctrl_errors	26.930s	621.111us	50	50	100.00
		lc_ctrl_security_escalation	16.760s	498.664us	50	50	100.00
		lc_ctrl_jtag_state_failure	2.142m	8.873ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	22.470s	3.177ms	20	20	100.00
		lc_ctrl_jtag_errors	1.933m	21.140ms	20	20	100.00
V2	jtag_access	lc_ctrl_jtag_smoke	11.060s	825.510us	20	20	100.00
		lc_ctrl_jtag_state_post_trans	31.580s	1.019ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	22.470s	3.177ms	20	20	100.00
		lc_ctrl_jtag_errors	1.933m	21.140ms	20	20	100.00
		lc_ctrl_jtag_access	25.160s	5.657ms	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	37.140s	7.284ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	6.370s	3.778ms	10	10	100.00
		lc_ctrl_jtag_csr_rw	3.180s	324.868us	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	39.210s	4.682ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	11.840s	2.049ms	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	1.800s	113.862us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	4.390s	201.590us	10	10	100.00
		lc_ctrl_jtag_alert_test	1.810s	47.410us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	1.213m	3.484ms	10	10	100.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.190s	44.988us	50	50	100.00
V2	stress_all	lc_ctrl_stress_all	7.236m	132.014ms	50	50	100.00
V2	alert_test	lc_ctrl_alert_test	1.350s	143.192us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	5.570s	314.108us	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	5.570s	314.108us	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.250s	34.148us	5	5	100.00
		lc_ctrl_csr_rw	1.150s	18.044us	20	20	100.00
		lc_ctrl_csr_aliasing	1.340s	23.592us	5	5	100.00
		lc_ctrl_same_csr_outstanding	2.030s	174.629us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.250s	34.148us	5	5	100.00
		lc_ctrl_csr_rw	1.150s	18.044us	20	20	100.00
		lc_ctrl_csr_aliasing	1.340s	23.592us	5	5	100.00
		lc_ctrl_same_csr_outstanding	2.030s	174.629us	20	20	100.00
V2		TOTAL			700	700	100.00
V2S	tl_intg_err	lc_ctrl_sec_cm	36.780s	340.476us	5	5	100.00
		lc_ctrl_tl_intg_err	4.620s	139.551us	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	4.620s	139.551us	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	22.410s	335.266us	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	35.680s	1.478ms	50	50	100.00
		lc_ctrl_sec_cm	36.780s	340.476us	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	35.680s	1.478ms	50	50	100.00
		lc_ctrl_sec_cm	36.780s	340.476us	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	35.680s	1.478ms	50	50	100.00
		lc_ctrl_sec_cm	36.780s	340.476us	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	35.680s	1.478ms	50	50	100.00
		lc_ctrl_sec_cm	36.780s	340.476us	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	35.680s	1.478ms	50	50	100.00
		lc_ctrl_sec_cm	36.780s	340.476us	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	35.680s	1.478ms	50	50	100.00
		lc_ctrl_sec_cm	36.780s	340.476us	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	35.680s	1.478ms	50	50	100.00
		lc_ctrl_sec_cm	36.780s	340.476us	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	35.680s	1.478ms	50	50	100.00
		lc_ctrl_sec_cm	36.780s	340.476us	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	16.760s	498.664us	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	11.250s	236.137us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	31.580s	1.019ms	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	23.990s	631.929us	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	23.990s	631.929us	50	50	100.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	18.600s	498.327us	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	20.460s	1.240ms	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	20.460s	1.240ms	50	50	100.00
V2S		TOTAL			175	175	100.00
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	2.941h	141.626ms	28	50	56.00
V3		TOTAL			28	50	56.00
		TOTAL			1008	1030	97.86

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	27	100.00
V2S	5	5	5	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.20	97.92	95.75	93.40	100.00	98.52	98.51	96.29

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:839) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 17 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 17 failures.

    • 0.lc_ctrl_stress_all_with_rand_reset.58853474455281429712825647754804288048353367635942277721658278404233915858974
      Line 34820, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/0.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 33586534645 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 33586534645 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 7.lc_ctrl_stress_all_with_rand_reset.33013544028316925029937459782103148395914862091992157419777336572739739376317
      Line 1385, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/7.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1672139159 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 1672139159 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 15 more failures.

• UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (* [*] vs * [*]) has 3 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 3 failures.

    • 2.lc_ctrl_stress_all_with_rand_reset.23586439140840683820778338695771344341885296224683408646732157069398707369812
      Line 1854, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/2.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 693253995 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 693253995 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 25.lc_ctrl_stress_all_with_rand_reset.113973853370231995535496448985922532901724180225605053046526937533857431416378
      Line 12764, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/25.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 37663977886 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 37663977886 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 1 more failures.

• UVM_ERROR (cip_base_vseq.sv:551) [lc_ctrl_common_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_state_error fired unexpectedly! has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 14.lc_ctrl_stress_all_with_rand_reset.15462636889740951162392409249934913064965154562868039964004988572516140072857
      Line 11015, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/14.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 47511998374 ps: (cip_base_vseq.sv:551) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
        UVM_INFO @ 47511998374 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Error-[CNST-STOF] Constraint solver timeout failure has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 37.lc_ctrl_stress_all_with_rand_reset.106861943739029248997613961898065815355555790263132059261444137932267468542248
      Line 57535, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/37.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        Error-[CNST-STOF] Constraint solver timeout failure
        ../src/lowrisc_dv_sec_cm_0/prim_sparse_fsm_flop_if.sv, 43
          Exceeded cpu time limit during solve.
          Please use the run-time switch +ntb_solver_cpu_limit to increase the cpu
          limit.  The default cpu limit is 1000 seconds per partition.
      

Past Results

• Latest
• 2024.07.24_08.12.50
• 2024.07.23_08.46.04
• 2024.07.22_08.45.02
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