LC_CTRL/VOLATILE_UNLOCK_DISABLED Simulation Results

Thursday July 25 2024 23:02:35 UTC

GitHub Revision: `a47820eb4c`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 42717125255024305080795900498886328747526075712606813106869971419713539568742

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	8.250s	584.157us	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.070s	14.396us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.150s	35.262us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	2.100s	94.501us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	1.300s	59.732us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	2.120s	26.696us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.150s	35.262us	20	20	100.00
		lc_ctrl_csr_aliasing	1.300s	59.732us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	11.630s	611.224us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	28.430s	3.473ms	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	1.060s	14.154us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	6.000s	548.216us	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	39.140s	1.105ms	50	50	100.00
V2	lc_errors	lc_ctrl_errors	18.390s	796.682us	48	50	96.00
V2	security_escalation	lc_ctrl_state_failure	39.140s	1.105ms	50	50	100.00
		lc_ctrl_prog_failure	6.000s	548.216us	50	50	100.00
		lc_ctrl_errors	18.390s	796.682us	48	50	96.00
		lc_ctrl_security_escalation	15.080s	1.610ms	50	50	100.00
		lc_ctrl_jtag_state_failure	1.992m	3.786ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	22.790s	1.133ms	20	20	100.00
		lc_ctrl_jtag_errors	2.102m	14.064ms	20	20	100.00
V2	jtag_access	lc_ctrl_jtag_smoke	18.570s	1.429ms	20	20	100.00
		lc_ctrl_jtag_state_post_trans	31.620s	10.415ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	22.790s	1.133ms	20	20	100.00
		lc_ctrl_jtag_errors	2.102m	14.064ms	20	20	100.00
		lc_ctrl_jtag_access	21.400s	986.035us	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	36.600s	1.464ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	4.050s	138.053us	10	10	100.00
		lc_ctrl_jtag_csr_rw	3.690s	156.251us	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	49.410s	17.350ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	17.400s	22.077ms	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	1.420s	91.436us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	4.450s	151.310us	10	10	100.00
		lc_ctrl_jtag_alert_test	2.600s	161.151us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	13.670s	2.060ms	9	10	90.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.300s	37.256us	50	50	100.00
V2	stress_all	lc_ctrl_stress_all	10.604m	32.238ms	50	50	100.00
V2	alert_test	lc_ctrl_alert_test	1.480s	30.889us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	5.940s	293.330us	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	5.940s	293.330us	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.070s	14.396us	5	5	100.00
		lc_ctrl_csr_rw	1.150s	35.262us	20	20	100.00
		lc_ctrl_csr_aliasing	1.300s	59.732us	5	5	100.00
		lc_ctrl_same_csr_outstanding	2.030s	44.844us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.070s	14.396us	5	5	100.00
		lc_ctrl_csr_rw	1.150s	35.262us	20	20	100.00
		lc_ctrl_csr_aliasing	1.300s	59.732us	5	5	100.00
		lc_ctrl_same_csr_outstanding	2.030s	44.844us	20	20	100.00
V2		TOTAL			697	700	99.57
V2S	tl_intg_err	lc_ctrl_sec_cm	41.030s	880.570us	5	5	100.00
		lc_ctrl_tl_intg_err	4.500s	107.196us	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	4.500s	107.196us	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	28.430s	3.473ms	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	39.140s	1.105ms	50	50	100.00
		lc_ctrl_sec_cm	41.030s	880.570us	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	39.140s	1.105ms	50	50	100.00
		lc_ctrl_sec_cm	41.030s	880.570us	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	39.140s	1.105ms	50	50	100.00
		lc_ctrl_sec_cm	41.030s	880.570us	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	39.140s	1.105ms	50	50	100.00
		lc_ctrl_sec_cm	41.030s	880.570us	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	39.140s	1.105ms	50	50	100.00
		lc_ctrl_sec_cm	41.030s	880.570us	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	39.140s	1.105ms	50	50	100.00
		lc_ctrl_sec_cm	41.030s	880.570us	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	39.140s	1.105ms	50	50	100.00
		lc_ctrl_sec_cm	41.030s	880.570us	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	39.140s	1.105ms	50	50	100.00
		lc_ctrl_sec_cm	41.030s	880.570us	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	15.080s	1.610ms	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	11.630s	611.224us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	31.620s	10.415ms	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	22.640s	1.348ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	22.640s	1.348ms	50	50	100.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	26.310s	6.574ms	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	20.560s	1.415ms	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	20.560s	1.415ms	50	50	100.00
V2S		TOTAL			175	175	100.00
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	30.617m	17.665ms	27	50	54.00
V3		TOTAL			27	50	54.00
		TOTAL			1004	1030	97.48

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	25	92.59
V2S	5	5	5	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.83	97.92	95.56	93.40	97.62	98.52	98.51	96.29

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:839) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 13 failures:
- Test lc_ctrl_stress_all_with_rand_reset has 13 failures.
  - 1.lc_ctrl_stress_all_with_rand_reset.49196182544709606835578390084742887675358295464599780891087628833873552462993
    Line 8800, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/1.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 34976477663 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 34976477663 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 9.lc_ctrl_stress_all_with_rand_reset.71482056680120760074163995149804929261210183208041366146005238122549572139271
    Line 12791, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/9.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 98120719360 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 98120719360 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 11 more failures.
Error-[CNST-STOF] Constraint solver timeout failure has 3 failures:
- Test lc_ctrl_stress_all_with_rand_reset has 3 failures.
  - 2.lc_ctrl_stress_all_with_rand_reset.36565491550378990033418259745438809421432101534123012420427675981259099720904
    Line 39254, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/2.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Error-[CNST-STOF] Constraint solver timeout failure
  ../src/lowrisc_dv_sec_cm_0/prim_sparse_fsm_flop_if.sv, 43
    Exceeded cpu time limit during solve.
    Please use the run-time switch +ntb_solver_cpu_limit to increase the cpu
    limit.  The default cpu limit is 1000 seconds per partition.
```
  - 40.lc_ctrl_stress_all_with_rand_reset.75266472214643173042670869210687635988402944442111993864703954300676755047400
    Line 28349, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/40.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Error-[CNST-STOF] Constraint solver timeout failure
  ../src/lowrisc_dv_sec_cm_0/prim_sparse_fsm_flop_if.sv, 43
    Exceeded cpu time limit during solve.
    Please use the run-time switch +ntb_solver_cpu_limit to increase the cpu
    limit.  The default cpu limit is 1000 seconds per partition.
```
  - ... and 1 more failures.
UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (* [*] vs * [*]) has 3 failures:
- Test lc_ctrl_stress_all_with_rand_reset has 2 failures.
  - 28.lc_ctrl_stress_all_with_rand_reset.74207327773278128396024997322974371311423229519881384792605977158330064468335
    Line 1690, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/28.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 19329695923 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 19329695923 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 49.lc_ctrl_stress_all_with_rand_reset.5620321065496579942823158496796865702639507653460889652099970390755682748272
    Line 11962, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/49.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 82247986671 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 82247986671 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test lc_ctrl_errors has 1 failures.
  - 41.lc_ctrl_errors.67809298839545636878227125871175458353608736142291993428142867194868781025046
    Line 1210, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/41.lc_ctrl_errors/latest/run.log
```
  UVM_ERROR @ 344505739 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 344505739 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:551) [lc_ctrl_smoke_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_prog_error fired unexpectedly! has 2 failures:
- Test lc_ctrl_stress_all_with_rand_reset has 2 failures.
  - 15.lc_ctrl_stress_all_with_rand_reset.107567051983645186917247620854489296219448280121117062128440161463086186531332
    Line 8269, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/15.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1681403811 ps: (cip_base_vseq.sv:551) [uvm_test_top.env.virtual_sequencer.lc_ctrl_smoke_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_prog_error fired unexpectedly!
  UVM_INFO @ 1681403811 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 25.lc_ctrl_stress_all_with_rand_reset.79149526950254537939209334914585538912823668223213261050577210648310332524967
    Line 528, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/25.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @  46953782 ps: (cip_base_vseq.sv:551) [uvm_test_top.env.virtual_sequencer.lc_ctrl_smoke_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_prog_error fired unexpectedly!
  UVM_INFO @  46953782 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:551) [lc_ctrl_common_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_state_error fired unexpectedly! has 2 failures:
- Test lc_ctrl_stress_all_with_rand_reset has 2 failures.
  - 34.lc_ctrl_stress_all_with_rand_reset.110019282876355515507856407860034569753766540269958808935052801347089044539769
    Line 26088, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/34.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 33837489526 ps: (cip_base_vseq.sv:551) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
  UVM_INFO @ 33837489526 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 47.lc_ctrl_stress_all_with_rand_reset.112427967757948451355939139093187065160731312663729943044166429137648682945288
    Line 16719, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/47.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 75159383151 ps: (cip_base_vseq.sv:551) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
  UVM_INFO @ 75159383151 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (lc_ctrl_jtag_priority_vseq.sv:113) [lc_ctrl_jtag_priority_vseq] timeout occurred! has 1 failures:
- Test lc_ctrl_jtag_priority has 1 failures.
  - 3.lc_ctrl_jtag_priority.31482815333830195339241031966087473260148472058994962856999126833976262319907
    Line 422, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/3.lc_ctrl_jtag_priority/latest/run.log
```
  UVM_FATAL @ 10014265231 ps: (lc_ctrl_jtag_priority_vseq.sv:113) [uvm_test_top.env.virtual_sequencer.lc_ctrl_jtag_priority_vseq] timeout occurred!
  UVM_INFO @ 10014265231 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_scoreboard.sv:301) scoreboard [scoreboard] alert fatal_prog_error did not trigger max_delay:* has 1 failures:
- Test lc_ctrl_stress_all_with_rand_reset has 1 failures.
  - 17.lc_ctrl_stress_all_with_rand_reset.57325971413535699512721694121461320873982303103675264768879883471799548282760
    Line 11256, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/17.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 13846794533 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
  UVM_INFO @ 13846794533 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (lc_ctrl_errors_vseq.sv:769) [lc_ctrl_lc_errors_vseq] Check failed otp_error_act == otp_error_exp (* [*] vs * [*]) has 1 failures:
- Test lc_ctrl_errors has 1 failures.
  - 37.lc_ctrl_errors.30845252726982079297705714532675203043681397063985655496341855476214393197684
    Line 2425, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/37.lc_ctrl_errors/latest/run.log
```
  UVM_ERROR @ 291130384 ps: (lc_ctrl_errors_vseq.sv:769) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed otp_error_act == otp_error_exp (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 291130384 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

LC_CTRL/VOLATILE_UNLOCK_DISABLED Simulation Results

Thursday July 25 2024 23:02:35 UTC

GitHub Revision: a47820eb4c

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 42717125255024305080795900498886328747526075712606813106869971419713539568742

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `a47820eb4c`