LC_CTRL/VOLATILE_UNLOCK_DISABLED Simulation Results

Friday July 26 2024 23:02:17 UTC

GitHub Revision: 4877b481e8

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 32772136499307530671572864311472020383177374948143841887013058662761887638244

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	8.790s	153.827us	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.140s	24.095us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.120s	27.512us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	1.630s	28.350us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	1.430s	74.497us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	1.990s	26.707us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.120s	27.512us	20	20	100.00
		lc_ctrl_csr_aliasing	1.430s	74.497us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	9.780s	650.334us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	18.810s	653.255us	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	1.030s	13.708us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	5.970s	289.614us	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	40.660s	353.049us	50	50	100.00
V2	lc_errors	lc_ctrl_errors	26.460s	695.491us	50	50	100.00
V2	security_escalation	lc_ctrl_state_failure	40.660s	353.049us	50	50	100.00
		lc_ctrl_prog_failure	5.970s	289.614us	50	50	100.00
		lc_ctrl_errors	26.460s	695.491us	50	50	100.00
		lc_ctrl_security_escalation	15.620s	3.131ms	50	50	100.00
		lc_ctrl_jtag_state_failure	1.889m	4.299ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	10.050s	1.117ms	20	20	100.00
		lc_ctrl_jtag_errors	1.716m	3.767ms	20	20	100.00
V2	jtag_access	lc_ctrl_jtag_smoke	19.740s	3.154ms	20	20	100.00
		lc_ctrl_jtag_state_post_trans	24.400s	2.271ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	10.050s	1.117ms	20	20	100.00
		lc_ctrl_jtag_errors	1.716m	3.767ms	20	20	100.00
		lc_ctrl_jtag_access	32.500s	1.481ms	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	40.420s	3.637ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	3.710s	943.396us	10	10	100.00
		lc_ctrl_jtag_csr_rw	2.510s	320.623us	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	22.930s	2.612ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	15.570s	660.675us	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	1.700s	177.041us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	3.880s	162.706us	10	10	100.00
		lc_ctrl_jtag_alert_test	2.260s	102.859us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	46.950s	12.828ms	10	10	100.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.210s	44.227us	50	50	100.00
V2	stress_all	lc_ctrl_stress_all	13.428m	36.982ms	50	50	100.00
V2	alert_test	lc_ctrl_alert_test	1.390s	78.847us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	5.720s	158.484us	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	5.720s	158.484us	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.140s	24.095us	5	5	100.00
		lc_ctrl_csr_rw	1.120s	27.512us	20	20	100.00
		lc_ctrl_csr_aliasing	1.430s	74.497us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.860s	47.839us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.140s	24.095us	5	5	100.00
		lc_ctrl_csr_rw	1.120s	27.512us	20	20	100.00
		lc_ctrl_csr_aliasing	1.430s	74.497us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.860s	47.839us	20	20	100.00
V2		TOTAL			700	700	100.00
V2S	tl_intg_err	lc_ctrl_sec_cm	39.100s	792.621us	5	5	100.00
		lc_ctrl_tl_intg_err	4.610s	290.220us	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	4.610s	290.220us	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	18.810s	653.255us	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	40.660s	353.049us	50	50	100.00
		lc_ctrl_sec_cm	39.100s	792.621us	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	40.660s	353.049us	50	50	100.00
		lc_ctrl_sec_cm	39.100s	792.621us	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	40.660s	353.049us	50	50	100.00
		lc_ctrl_sec_cm	39.100s	792.621us	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	40.660s	353.049us	50	50	100.00
		lc_ctrl_sec_cm	39.100s	792.621us	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	40.660s	353.049us	50	50	100.00
		lc_ctrl_sec_cm	39.100s	792.621us	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	40.660s	353.049us	50	50	100.00
		lc_ctrl_sec_cm	39.100s	792.621us	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	40.660s	353.049us	50	50	100.00
		lc_ctrl_sec_cm	39.100s	792.621us	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	40.660s	353.049us	50	50	100.00
		lc_ctrl_sec_cm	39.100s	792.621us	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	15.620s	3.131ms	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	9.780s	650.334us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	24.400s	2.271ms	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	19.680s	477.093us	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	19.680s	477.093us	50	50	100.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	24.740s	3.766ms	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	18.230s	2.288ms	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	18.230s	2.288ms	50	50	100.00
V2S		TOTAL			175	175	100.00
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	40.569m	176.271ms	27	50	54.00
V3		TOTAL			27	50	54.00
		TOTAL			1007	1030	97.77

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	27	100.00
V2S	5	5	5	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.16	97.92	95.66	93.40	100.00	98.52	98.51	96.11

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:839) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 20 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 20 failures.

    • 0.lc_ctrl_stress_all_with_rand_reset.3983035155504221219017163068789117159000662283386574494256878734597855742831
      Line 2986, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/0.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 73291413404 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 73291413404 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 2.lc_ctrl_stress_all_with_rand_reset.3527452104518135576184200974387628342236185302074723058160752279922355670658
      Line 14623, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/2.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 27110773513 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 27110773513 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 18 more failures.

• UVM_ERROR (cip_base_scoreboard.sv:301) scoreboard [scoreboard] alert fatal_prog_error did not trigger max_delay:* has 2 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 2 failures.

    • 8.lc_ctrl_stress_all_with_rand_reset.113969767669285338134245367656765679650715819950128822749930148759507365007777
      Line 12034, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/8.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 4091768226 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 4091768226 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 45.lc_ctrl_stress_all_with_rand_reset.18841009857612862220225440764575154741940243959065837954795369744846066147525
      Line 4273, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/45.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 22484999268 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 22484999268 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:551) [lc_ctrl_common_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_state_error fired unexpectedly! has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 34.lc_ctrl_stress_all_with_rand_reset.47295845387251684508789220175835083518262330736825238555855104597998547043152
      Line 14440, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/34.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 19952994006 ps: (cip_base_vseq.sv:551) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
        UVM_INFO @ 19952994006 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

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