LC_CTRL/VOLATILE_UNLOCK_DISABLED Simulation Results

Saturday July 27 2024 23:02:25 UTC

GitHub Revision: eca25c0ff8

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 6528518538521148567139195500524222710943459299328477504124649113671643189924

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	7.590s	706.781us	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.300s	71.805us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.160s	17.151us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	1.790s	667.285us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	1.360s	63.184us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	2.430s	36.277us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.160s	17.151us	20	20	100.00
		lc_ctrl_csr_aliasing	1.360s	63.184us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	11.150s	748.393us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	21.710s	1.110ms	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	0.960s	12.048us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	5.660s	278.219us	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	42.220s	339.152us	50	50	100.00
V2	lc_errors	lc_ctrl_errors	23.990s	1.556ms	50	50	100.00
V2	security_escalation	lc_ctrl_state_failure	42.220s	339.152us	50	50	100.00
		lc_ctrl_prog_failure	5.660s	278.219us	50	50	100.00
		lc_ctrl_errors	23.990s	1.556ms	50	50	100.00
		lc_ctrl_security_escalation	17.690s	3.032ms	50	50	100.00
		lc_ctrl_jtag_state_failure	1.890m	9.525ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	18.050s	2.588ms	20	20	100.00
		lc_ctrl_jtag_errors	1.187m	2.399ms	20	20	100.00
V2	jtag_access	lc_ctrl_jtag_smoke	15.780s	1.222ms	20	20	100.00
		lc_ctrl_jtag_state_post_trans	38.770s	6.070ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	18.050s	2.588ms	20	20	100.00
		lc_ctrl_jtag_errors	1.187m	2.399ms	20	20	100.00
		lc_ctrl_jtag_access	32.220s	4.790ms	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	34.720s	4.691ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	3.950s	139.882us	10	10	100.00
		lc_ctrl_jtag_csr_rw	3.280s	119.373us	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	30.160s	2.619ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	26.350s	2.328ms	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	1.890s	39.962us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	4.490s	231.311us	10	10	100.00
		lc_ctrl_jtag_alert_test	2.170s	124.497us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	11.570s	418.215us	10	10	100.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.300s	16.900us	50	50	100.00
V2	stress_all	lc_ctrl_stress_all	7.750m	60.234ms	47	50	94.00
V2	alert_test	lc_ctrl_alert_test	1.480s	31.234us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	5.280s	139.456us	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	5.280s	139.456us	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.300s	71.805us	5	5	100.00
		lc_ctrl_csr_rw	1.160s	17.151us	20	20	100.00
		lc_ctrl_csr_aliasing	1.360s	63.184us	5	5	100.00
		lc_ctrl_same_csr_outstanding	2.130s	361.179us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.300s	71.805us	5	5	100.00
		lc_ctrl_csr_rw	1.160s	17.151us	20	20	100.00
		lc_ctrl_csr_aliasing	1.360s	63.184us	5	5	100.00
		lc_ctrl_same_csr_outstanding	2.130s	361.179us	20	20	100.00
V2		TOTAL			697	700	99.57
V2S	tl_intg_err	lc_ctrl_sec_cm	36.630s	212.183us	5	5	100.00
		lc_ctrl_tl_intg_err	5.410s	309.465us	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	5.410s	309.465us	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	21.710s	1.110ms	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	42.220s	339.152us	50	50	100.00
		lc_ctrl_sec_cm	36.630s	212.183us	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	42.220s	339.152us	50	50	100.00
		lc_ctrl_sec_cm	36.630s	212.183us	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	42.220s	339.152us	50	50	100.00
		lc_ctrl_sec_cm	36.630s	212.183us	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	42.220s	339.152us	50	50	100.00
		lc_ctrl_sec_cm	36.630s	212.183us	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	42.220s	339.152us	50	50	100.00
		lc_ctrl_sec_cm	36.630s	212.183us	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	42.220s	339.152us	50	50	100.00
		lc_ctrl_sec_cm	36.630s	212.183us	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	42.220s	339.152us	50	50	100.00
		lc_ctrl_sec_cm	36.630s	212.183us	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	42.220s	339.152us	50	50	100.00
		lc_ctrl_sec_cm	36.630s	212.183us	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	17.690s	3.032ms	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	11.150s	748.393us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	38.770s	6.070ms	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	26.990s	2.648ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	26.990s	2.648ms	50	50	100.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	27.720s	2.214ms	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	22.430s	750.790us	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	22.430s	750.790us	50	50	100.00
V2S		TOTAL			175	175	100.00
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	48.268m	3.585ms	25	50	50.00
V3		TOTAL			25	50	50.00
		TOTAL			1002	1030	97.28

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	26	96.30
V2S	5	5	5	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.87	97.92	95.84	93.40	97.62	98.52	98.51	96.29

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:839) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 19 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 19 failures.

    • 2.lc_ctrl_stress_all_with_rand_reset.89237849727138154828044907584721236546395035362551243308362249318660392670662
      Line 38348, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/2.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 213583495629 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 213583495629 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 5.lc_ctrl_stress_all_with_rand_reset.71455879928623955521247627693836381630735552749217674402693026634744883097968
      Line 17944, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/5.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 89924702152 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 89924702152 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 17 more failures.

• UVM_ERROR (cip_base_scoreboard.sv:301) scoreboard [scoreboard] alert fatal_prog_error did not trigger max_delay:* has 5 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 2 failures.

    • 10.lc_ctrl_stress_all_with_rand_reset.108438384973002237140745923204695317819497301374054111951396599085110161857833
      Line 32935, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/10.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 128023121083 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 128023121083 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 17.lc_ctrl_stress_all_with_rand_reset.56195544233779679127906800867528687143274852076949240379297616759840669902818
      Line 20706, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/17.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 11130323557 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 11130323557 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test lc_ctrl_stress_all has 3 failures.

    • 28.lc_ctrl_stress_all.31377208577644149700656983296202936734966450243457315927208743252575816637797
      Line 9078, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/28.lc_ctrl_stress_all/latest/run.log

        UVM_ERROR @ 168119507734 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 168119507734 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 35.lc_ctrl_stress_all.46564493938115180853219464681943782403974817671799781996285598950389580789448
      Line 3916, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/35.lc_ctrl_stress_all/latest/run.log

        UVM_ERROR @ 8749231818 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 8749231818 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 1 more failures.

• Error-[CNST-STOF] Constraint solver timeout failure has 2 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 2 failures.

    • 36.lc_ctrl_stress_all_with_rand_reset.54130592048632651897780745187012824145259993356067756292302962520859823300567
      Line 52051, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/36.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        Error-[CNST-STOF] Constraint solver timeout failure
        ../src/lowrisc_dv_sec_cm_0/prim_sparse_fsm_flop_if.sv, 43
          Exceeded cpu time limit during solve.
          Please use the run-time switch +ntb_solver_cpu_limit to increase the cpu
          limit.  The default cpu limit is 1000 seconds per partition.
      

    • 41.lc_ctrl_stress_all_with_rand_reset.53221369091951476721111177926344032122181280985266024411195502631650243318514
      Line 37032, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/41.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        Error-[CNST-STOF] Constraint solver timeout failure
        ../src/lowrisc_dv_sec_cm_0/prim_sparse_fsm_flop_if.sv, 43
          Exceeded cpu time limit during solve.
          Please use the run-time switch +ntb_solver_cpu_limit to increase the cpu
          limit.  The default cpu limit is 1000 seconds per partition.
      

• UVM_ERROR (lc_ctrl_errors_vseq.sv:762) [lc_ctrl_lc_errors_vseq] Check failed state_error_act == state_error_exp (* [*] vs * [*]) has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 26.lc_ctrl_stress_all_with_rand_reset.17984265696017358983501852925307852957761877533163539783074246523711840480931
      Line 13441, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/26.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 34827400355 ps: (lc_ctrl_errors_vseq.sv:762) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed state_error_act == state_error_exp (1 [0x1] vs 0 [0x0])
        UVM_INFO @ 34827400355 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:551) [lc_ctrl_common_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_state_error fired unexpectedly! has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 30.lc_ctrl_stress_all_with_rand_reset.61678616913434435915861474982081777598152545902435647983713138184302372834242
      Line 34951, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/30.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 68425362022 ps: (cip_base_vseq.sv:551) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
        UVM_INFO @ 68425362022 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

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