LC_CTRL/VOLATILE_UNLOCK_DISABLED Simulation Results

Sunday July 28 2024 23:02:28 UTC

GitHub Revision: eca25c0ff8

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 35694793988142953409419697382868702825984401131209466119932029294128690866559

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	15.500s	853.224us	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	0.960s	22.220us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.090s	15.682us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	1.510s	56.040us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	1.550s	115.933us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	1.740s	23.316us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.090s	15.682us	20	20	100.00
		lc_ctrl_csr_aliasing	1.550s	115.933us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	10.510s	1.970ms	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	26.190s	2.786ms	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	0.970s	61.852us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	4.290s	369.501us	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	40.560s	1.588ms	50	50	100.00
V2	lc_errors	lc_ctrl_errors	22.870s	769.913us	49	50	98.00
V2	security_escalation	lc_ctrl_state_failure	40.560s	1.588ms	50	50	100.00
		lc_ctrl_prog_failure	4.290s	369.501us	50	50	100.00
		lc_ctrl_errors	22.870s	769.913us	49	50	98.00
		lc_ctrl_security_escalation	21.320s	953.671us	50	50	100.00
		lc_ctrl_jtag_state_failure	2.121m	4.407ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	17.490s	575.701us	20	20	100.00
		lc_ctrl_jtag_errors	2.363m	10.582ms	20	20	100.00
V2	jtag_access	lc_ctrl_jtag_smoke	13.210s	876.517us	20	20	100.00
		lc_ctrl_jtag_state_post_trans	26.510s	1.599ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	17.490s	575.701us	20	20	100.00
		lc_ctrl_jtag_errors	2.363m	10.582ms	20	20	100.00
		lc_ctrl_jtag_access	23.520s	12.372ms	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	36.990s	1.249ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	5.300s	425.647us	10	10	100.00
		lc_ctrl_jtag_csr_rw	3.940s	872.773us	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	45.120s	4.101ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	13.020s	3.813ms	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	1.800s	38.607us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	5.580s	975.785us	10	10	100.00
		lc_ctrl_jtag_alert_test	1.810s	221.623us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	13.250s	513.234us	10	10	100.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.230s	21.532us	50	50	100.00
V2	stress_all	lc_ctrl_stress_all	11.729m	85.165ms	50	50	100.00
V2	alert_test	lc_ctrl_alert_test	1.620s	160.003us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	5.090s	567.658us	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	5.090s	567.658us	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	0.960s	22.220us	5	5	100.00
		lc_ctrl_csr_rw	1.090s	15.682us	20	20	100.00
		lc_ctrl_csr_aliasing	1.550s	115.933us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.910s	49.943us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	0.960s	22.220us	5	5	100.00
		lc_ctrl_csr_rw	1.090s	15.682us	20	20	100.00
		lc_ctrl_csr_aliasing	1.550s	115.933us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.910s	49.943us	20	20	100.00
V2		TOTAL			699	700	99.86
V2S	tl_intg_err	lc_ctrl_sec_cm	41.480s	2.524ms	5	5	100.00
		lc_ctrl_tl_intg_err	4.470s	453.219us	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	4.470s	453.219us	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	26.190s	2.786ms	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	40.560s	1.588ms	50	50	100.00
		lc_ctrl_sec_cm	41.480s	2.524ms	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	40.560s	1.588ms	50	50	100.00
		lc_ctrl_sec_cm	41.480s	2.524ms	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	40.560s	1.588ms	50	50	100.00
		lc_ctrl_sec_cm	41.480s	2.524ms	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	40.560s	1.588ms	50	50	100.00
		lc_ctrl_sec_cm	41.480s	2.524ms	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	40.560s	1.588ms	50	50	100.00
		lc_ctrl_sec_cm	41.480s	2.524ms	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	40.560s	1.588ms	50	50	100.00
		lc_ctrl_sec_cm	41.480s	2.524ms	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	40.560s	1.588ms	50	50	100.00
		lc_ctrl_sec_cm	41.480s	2.524ms	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	40.560s	1.588ms	50	50	100.00
		lc_ctrl_sec_cm	41.480s	2.524ms	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	21.320s	953.671us	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	10.510s	1.970ms	50	50	100.00
		lc_ctrl_jtag_state_post_trans	26.510s	1.599ms	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	21.590s	913.961us	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	21.590s	913.961us	50	50	100.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	23.680s	8.491ms	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	18.850s	2.320ms	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	18.850s	2.320ms	50	50	100.00
V2S		TOTAL			175	175	100.00
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	1.491h	308.090ms	27	50	54.00
V3		TOTAL			27	50	54.00
		TOTAL			1006	1030	97.67

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	26	96.30
V2S	5	5	5	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.13	97.92	95.66	93.40	100.00	98.52	98.51	95.94

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:839) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 17 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 17 failures.

    • 2.lc_ctrl_stress_all_with_rand_reset.41225723106432134606019287921320982193387818288228036143537644488963305378195
      Line 18359, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/2.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 20991722345 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 20991722345 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 4.lc_ctrl_stress_all_with_rand_reset.30542047155020944481325808495862938636969598542666892335236486954776091617913
      Line 8515, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/4.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 3807866090 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 3807866090 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 15 more failures.

• UVM_ERROR (cip_base_vseq.sv:551) [lc_ctrl_common_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_state_error fired unexpectedly! has 2 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 2 failures.

    • 1.lc_ctrl_stress_all_with_rand_reset.74198161287421505156906927389869783617692259313952856346383257345355132252804
      Line 40462, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/1.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 112059984366 ps: (cip_base_vseq.sv:551) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
        UVM_INFO @ 112059984366 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 27.lc_ctrl_stress_all_with_rand_reset.2235179140472547579201529274450170140282321781807595318307165106040624609651
      Line 39284, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/27.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 40927187663 ps: (cip_base_vseq.sv:551) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
        UVM_INFO @ 40927187663 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_scoreboard.sv:301) scoreboard [scoreboard] alert fatal_prog_error did not trigger max_delay:* has 2 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 2 failures.

    • 26.lc_ctrl_stress_all_with_rand_reset.28032507475978896064088675803707471745836840469693799416720575157390967967896
      Line 15135, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/26.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 44628872689 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 44628872689 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 45.lc_ctrl_stress_all_with_rand_reset.31303595185254758636082062090075241578255096196890104508558605109194737311266
      Line 5804, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/45.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 6663406530 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 6663406530 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Error-[CNST-STOF] Constraint solver timeout failure has 2 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 2 failures.

    • 34.lc_ctrl_stress_all_with_rand_reset.10789601719966476824264026976611564666517988258111490195581481835067977438690
      Line 44171, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/34.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        Error-[CNST-STOF] Constraint solver timeout failure
        ../src/lowrisc_dv_sec_cm_0/prim_sparse_fsm_flop_if.sv, 43
          Exceeded cpu time limit during solve.
          Please use the run-time switch +ntb_solver_cpu_limit to increase the cpu
          limit.  The default cpu limit is 1000 seconds per partition.
      

    • 35.lc_ctrl_stress_all_with_rand_reset.91159258672987806713114602360316373737603601339955929866125913896236637544830
      Line 44693, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/35.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        Error-[CNST-STOF] Constraint solver timeout failure
        ../src/lowrisc_dv_sec_cm_0/prim_sparse_fsm_flop_if.sv, 43
          Exceeded cpu time limit during solve.
          Please use the run-time switch +ntb_solver_cpu_limit to increase the cpu
          limit.  The default cpu limit is 1000 seconds per partition.
      

• UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (* [*] vs * [*]) has 1 failures:

  • Test lc_ctrl_errors has 1 failures.

    • 40.lc_ctrl_errors.46999185055378982959582300146827522187932409723311794546710847340334929838006
      Line 1112, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/40.lc_ctrl_errors/latest/run.log

        UVM_ERROR @ 379289555 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 379289555 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

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