LC_CTRL/VOLATILE_UNLOCK_DISABLED Simulation Results

Monday July 29 2024 23:02:32 UTC

GitHub Revision: 39f3866b56

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 91682663165753342493852681547271085771042321116470426223748766059309541455602

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	8.530s	149.062us	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.000s	64.666us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.130s	15.971us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	1.960s	85.776us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	1.610s	326.349us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	2.070s	31.050us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.130s	15.971us	20	20	100.00
		lc_ctrl_csr_aliasing	1.610s	326.349us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	10.520s	574.640us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	22.580s	675.896us	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	1.000s	17.529us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	7.010s	333.458us	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	36.570s	261.989us	50	50	100.00
V2	lc_errors	lc_ctrl_errors	28.470s	1.299ms	50	50	100.00
V2	security_escalation	lc_ctrl_state_failure	36.570s	261.989us	50	50	100.00
		lc_ctrl_prog_failure	7.010s	333.458us	50	50	100.00
		lc_ctrl_errors	28.470s	1.299ms	50	50	100.00
		lc_ctrl_security_escalation	19.510s	4.804ms	50	50	100.00
		lc_ctrl_jtag_state_failure	1.965m	14.212ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	19.090s	675.187us	20	20	100.00
		lc_ctrl_jtag_errors	1.745m	7.804ms	19	20	95.00
V2	jtag_access	lc_ctrl_jtag_smoke	20.470s	800.618us	20	20	100.00
		lc_ctrl_jtag_state_post_trans	28.710s	800.027us	20	20	100.00
		lc_ctrl_jtag_prog_failure	19.090s	675.187us	20	20	100.00
		lc_ctrl_jtag_errors	1.745m	7.804ms	19	20	95.00
		lc_ctrl_jtag_access	21.270s	3.501ms	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	41.600s	1.500ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	3.760s	150.321us	10	10	100.00
		lc_ctrl_jtag_csr_rw	4.650s	746.235us	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	50.810s	2.352ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	14.190s	3.304ms	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	1.980s	41.882us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	5.140s	423.762us	10	10	100.00
		lc_ctrl_jtag_alert_test	2.500s	75.679us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	45.330s	2.029ms	10	10	100.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.520s	30.074us	50	50	100.00
V2	stress_all	lc_ctrl_stress_all	12.755m	102.622ms	50	50	100.00
V2	alert_test	lc_ctrl_alert_test	1.390s	31.758us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	3.840s	512.195us	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	3.840s	512.195us	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.000s	64.666us	5	5	100.00
		lc_ctrl_csr_rw	1.130s	15.971us	20	20	100.00
		lc_ctrl_csr_aliasing	1.610s	326.349us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.660s	189.966us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.000s	64.666us	5	5	100.00
		lc_ctrl_csr_rw	1.130s	15.971us	20	20	100.00
		lc_ctrl_csr_aliasing	1.610s	326.349us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.660s	189.966us	20	20	100.00
V2		TOTAL			699	700	99.86
V2S	tl_intg_err	lc_ctrl_sec_cm	37.310s	905.242us	5	5	100.00
		lc_ctrl_tl_intg_err	3.650s	174.647us	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	3.650s	174.647us	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	22.580s	675.896us	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	36.570s	261.989us	50	50	100.00
		lc_ctrl_sec_cm	37.310s	905.242us	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	36.570s	261.989us	50	50	100.00
		lc_ctrl_sec_cm	37.310s	905.242us	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	36.570s	261.989us	50	50	100.00
		lc_ctrl_sec_cm	37.310s	905.242us	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	36.570s	261.989us	50	50	100.00
		lc_ctrl_sec_cm	37.310s	905.242us	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	36.570s	261.989us	50	50	100.00
		lc_ctrl_sec_cm	37.310s	905.242us	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	36.570s	261.989us	50	50	100.00
		lc_ctrl_sec_cm	37.310s	905.242us	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	36.570s	261.989us	50	50	100.00
		lc_ctrl_sec_cm	37.310s	905.242us	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	36.570s	261.989us	50	50	100.00
		lc_ctrl_sec_cm	37.310s	905.242us	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	19.510s	4.804ms	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	10.520s	574.640us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	28.710s	800.027us	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	23.800s	576.380us	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	23.800s	576.380us	50	50	100.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	23.380s	5.551ms	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	19.630s	625.344us	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	19.630s	625.344us	50	50	100.00
V2S		TOTAL			175	175	100.00
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	47.033m	43.042ms	22	50	44.00
V3		TOTAL			22	50	44.00
		TOTAL			1001	1030	97.18

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	26	96.30
V2S	5	5	5	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.25	97.92	96.12	93.40	100.00	98.52	98.51	96.29

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:836) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 20 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 20 failures.

    • 2.lc_ctrl_stress_all_with_rand_reset.52662548164226465538633776899867987968660951900103919797482404793944461103514
      Line 21001, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/2.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 49233765627 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 49233765627 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 4.lc_ctrl_stress_all_with_rand_reset.28424476561941110187203297130600668501782405907491460044620190435765347161026
      Line 7128, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/4.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 9031590198 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 9031590198 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 18 more failures.

• UVM_ERROR (cip_base_scoreboard.sv:301) scoreboard [scoreboard] alert fatal_prog_error did not trigger max_delay:* has 4 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 4 failures.

    • 3.lc_ctrl_stress_all_with_rand_reset.10603375999085439973819869253678411247473833441079744626717442874018806483039
      Line 17550, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/3.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 52833884352 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 52833884352 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 17.lc_ctrl_stress_all_with_rand_reset.93985047047066782658801389712023701026908095895716285562921650370942275641712
      Line 21435, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/17.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 188995987699 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 188995987699 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 2 more failures.

• UVM_ERROR (cip_base_vseq.sv:548) [lc_ctrl_common_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_state_error fired unexpectedly! has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 12.lc_ctrl_stress_all_with_rand_reset.12954175201496503166434557778728235916758258399458710629445118975562114392896
      Line 21991, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/12.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 5276823111 ps: (cip_base_vseq.sv:548) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
        UVM_INFO @ 5276823111 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (lc_ctrl_scoreboard.sv:243) [scoreboard] Check failed cfg.lc_ctrl_vif.lc_escalate_en_o == exp_o.lc_escalate_en_o (* [*] vs * [*]) Called from line: *, LC_St DecLcStTestLocked* has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 15.lc_ctrl_stress_all_with_rand_reset.19083474238110367240582363732434574127489783767890653635311001771964755557869
      Line 23683, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/15.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 81728822741 ps: (lc_ctrl_scoreboard.sv:243) [uvm_test_top.env.scoreboard] Check failed cfg.lc_ctrl_vif.lc_escalate_en_o == exp_o.lc_escalate_en_o (10 [0xa] vs 5 [0x5]) Called from line: 100, LC_St DecLcStTestLocked3
        UVM_INFO @ 81728822741 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (* [*] vs * [*]) has 1 failures:

  • Test lc_ctrl_jtag_errors has 1 failures.

    • 18.lc_ctrl_jtag_errors.60527868852577956169902797826845611752880230585190685564283480078473770133833
      Line 1808, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/18.lc_ctrl_jtag_errors/latest/run.log

        UVM_ERROR @ 1674297333 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 1674297333 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Job lc_ctrl_volatile_unlock_disabled-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 26.lc_ctrl_stress_all_with_rand_reset.102950971876362841589634835584549744859159830671346793261897572782995896145194
      Log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/26.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        Job ID: smart:329b74cb-b7fd-4bce-a3d4-133d5b3805c6
      

• Error-[CNST-STOF] Constraint solver timeout failure has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 43.lc_ctrl_stress_all_with_rand_reset.57570410002203901658372927288206051040395702309224818938457364423261650191278
      Line 23724, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/43.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        Error-[CNST-STOF] Constraint solver timeout failure
        ../src/lowrisc_dv_sec_cm_0/prim_sparse_fsm_flop_if.sv, 43
          Exceeded cpu time limit during solve.
          Please use the run-time switch +ntb_solver_cpu_limit to increase the cpu
          limit.  The default cpu limit is 1000 seconds per partition.
      

Past Results

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