LC_CTRL/VOLATILE_UNLOCK_DISABLED Simulation Results

Tuesday July 30 2024 23:02:08 UTC

GitHub Revision: `fdfa12db04`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 101467584611478134588291649782725219255540557286164709436567235390830780957271

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	9.260s	650.991us	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.340s	21.304us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.110s	15.293us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	2.790s	69.804us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	1.300s	32.488us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	1.960s	51.267us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.110s	15.293us	20	20	100.00
		lc_ctrl_csr_aliasing	1.300s	32.488us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	9.590s	300.519us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	19.410s	1.490ms	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	1.040s	13.096us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	5.270s	120.930us	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	35.300s	244.036us	50	50	100.00
V2	lc_errors	lc_ctrl_errors	27.080s	2.724ms	50	50	100.00
V2	security_escalation	lc_ctrl_state_failure	35.300s	244.036us	50	50	100.00
		lc_ctrl_prog_failure	5.270s	120.930us	50	50	100.00
		lc_ctrl_errors	27.080s	2.724ms	50	50	100.00
		lc_ctrl_security_escalation	16.020s	583.714us	50	50	100.00
		lc_ctrl_jtag_state_failure	1.839m	14.595ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	26.080s	5.169ms	20	20	100.00
		lc_ctrl_jtag_errors	2.288m	10.147ms	20	20	100.00
V2	jtag_access	lc_ctrl_jtag_smoke	20.020s	2.931ms	20	20	100.00
		lc_ctrl_jtag_state_post_trans	39.730s	1.318ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	26.080s	5.169ms	20	20	100.00
		lc_ctrl_jtag_errors	2.288m	10.147ms	20	20	100.00
		lc_ctrl_jtag_access	26.000s	1.257ms	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	39.560s	1.560ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	5.230s	850.816us	10	10	100.00
		lc_ctrl_jtag_csr_rw	2.460s	323.417us	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	34.970s	6.300ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	25.540s	1.157ms	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	2.130s	899.540us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	6.320s	978.084us	10	10	100.00
		lc_ctrl_jtag_alert_test	2.160s	57.455us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	26.880s	15.836ms	10	10	100.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.300s	54.210us	49	50	98.00
V2	stress_all	lc_ctrl_stress_all	8.313m	69.154ms	48	50	96.00
V2	alert_test	lc_ctrl_alert_test	1.290s	63.090us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	4.810s	209.750us	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	4.810s	209.750us	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.340s	21.304us	5	5	100.00
		lc_ctrl_csr_rw	1.110s	15.293us	20	20	100.00
		lc_ctrl_csr_aliasing	1.300s	32.488us	5	5	100.00
		lc_ctrl_same_csr_outstanding	2.120s	294.424us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.340s	21.304us	5	5	100.00
		lc_ctrl_csr_rw	1.110s	15.293us	20	20	100.00
		lc_ctrl_csr_aliasing	1.300s	32.488us	5	5	100.00
		lc_ctrl_same_csr_outstanding	2.120s	294.424us	20	20	100.00
V2		TOTAL			697	700	99.57
V2S	tl_intg_err	lc_ctrl_sec_cm	39.170s	210.746us	5	5	100.00
		lc_ctrl_tl_intg_err	4.560s	485.317us	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	4.560s	485.317us	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	19.410s	1.490ms	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	35.300s	244.036us	50	50	100.00
		lc_ctrl_sec_cm	39.170s	210.746us	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	35.300s	244.036us	50	50	100.00
		lc_ctrl_sec_cm	39.170s	210.746us	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	35.300s	244.036us	50	50	100.00
		lc_ctrl_sec_cm	39.170s	210.746us	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	35.300s	244.036us	50	50	100.00
		lc_ctrl_sec_cm	39.170s	210.746us	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	35.300s	244.036us	50	50	100.00
		lc_ctrl_sec_cm	39.170s	210.746us	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	35.300s	244.036us	50	50	100.00
		lc_ctrl_sec_cm	39.170s	210.746us	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	35.300s	244.036us	50	50	100.00
		lc_ctrl_sec_cm	39.170s	210.746us	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	35.300s	244.036us	50	50	100.00
		lc_ctrl_sec_cm	39.170s	210.746us	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	16.020s	583.714us	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	9.590s	300.519us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	39.730s	1.318ms	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	25.890s	10.254ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	25.890s	10.254ms	50	50	100.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	27.310s	739.085us	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	18.420s	1.156ms	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	18.420s	1.156ms	50	50	100.00
V2S		TOTAL			175	175	100.00
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	2.536h	82.450ms	20	50	40.00
V3		TOTAL			20	50	40.00
		TOTAL			997	1030	96.80

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	25	92.59
V2S	5	5	5	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.90	97.92	96.03	93.40	97.62	98.52	98.51	96.29

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:836) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 23 failures:
- Test lc_ctrl_stress_all_with_rand_reset has 23 failures.
  - 1.lc_ctrl_stress_all_with_rand_reset.67794334294611672486351520295449606919828771710447601494106056372225025783717
    Line 48038, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/1.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 91533118557 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 91533118557 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 3.lc_ctrl_stress_all_with_rand_reset.54632652993066399847575353758249491054713793311971358221747748799433172462211
    Line 46079, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/3.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 359763602557 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 359763602557 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 21 more failures.
Error-[CNST-STOF] Constraint solver timeout failure has 2 failures:
- Test lc_ctrl_stress_all_with_rand_reset has 2 failures.
  - 4.lc_ctrl_stress_all_with_rand_reset.105533065933198654607648848805494173971388428292639480103337680049385209017904
    Line 38088, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/4.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Error-[CNST-STOF] Constraint solver timeout failure
  ../src/lowrisc_dv_sec_cm_0/prim_sparse_fsm_flop_if.sv, 43
    Exceeded cpu time limit during solve.
    Please use the run-time switch +ntb_solver_cpu_limit to increase the cpu
    limit.  The default cpu limit is 1000 seconds per partition.
```
  - 17.lc_ctrl_stress_all_with_rand_reset.22708616979797202176616380603202168557721320311973901172451307701024695758286
    Line 51583, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/17.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Error-[CNST-STOF] Constraint solver timeout failure
  ../src/lowrisc_dv_sec_cm_0/prim_sparse_fsm_flop_if.sv, 43
    Exceeded cpu time limit during solve.
    Please use the run-time switch +ntb_solver_cpu_limit to increase the cpu
    limit.  The default cpu limit is 1000 seconds per partition.
```
UVM_ERROR (cip_base_scoreboard.sv:301) scoreboard [scoreboard] alert fatal_prog_error did not trigger max_delay:* has 2 failures:
- Test lc_ctrl_stress_all_with_rand_reset has 2 failures.
  - 7.lc_ctrl_stress_all_with_rand_reset.64726529162293245861252838495829734361845366638820108726722162196741986735093
    Line 2818, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/7.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 10339649499 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
  UVM_INFO @ 10339649499 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 21.lc_ctrl_stress_all_with_rand_reset.47691471554399831964208766197415079767727212826568116308298541832178594413169
    Line 36888, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/21.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 127530980302 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
  UVM_INFO @ 127530980302 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (lc_ctrl_scoreboard.sv:238) [scoreboard] Check failed cfg.lc_ctrl_vif.lc_dft_en_o == exp_o.lc_dft_en_o (* [*] vs * [*]) Called from line: *, LC_St DecLcStTestUnlocked* has 1 failures:
- Test lc_ctrl_stress_all_with_rand_reset has 1 failures.
  - 9.lc_ctrl_stress_all_with_rand_reset.71443330805284902951482552556705549457452441071822080855292037117777668929784
    Line 17779, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/9.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 6921164738 ps: (lc_ctrl_scoreboard.sv:238) [uvm_test_top.env.scoreboard] Check failed cfg.lc_ctrl_vif.lc_dft_en_o == exp_o.lc_dft_en_o (5 [0x5] vs 10 [0xa]) Called from line: 100, LC_St DecLcStTestUnlocked6
  UVM_INFO @ 6921164738 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (lc_ctrl_errors_vseq.sv:769) [lc_ctrl_lc_errors_vseq] Check failed otp_error_act == otp_error_exp (* [*] vs * [*]) has 1 failures:
- Test lc_ctrl_stress_all has 1 failures.
  - 15.lc_ctrl_stress_all.108354449731883276777907132335947728452160235352297616971038369651618026487583
    Line 6935, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/15.lc_ctrl_stress_all/latest/run.log
```
  UVM_ERROR @ 501777201 ps: (lc_ctrl_errors_vseq.sv:769) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed otp_error_act == otp_error_exp (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 501777201 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (* [*] vs * [*]) has 1 failures:
- Test lc_ctrl_stress_all has 1 failures.
  - 17.lc_ctrl_stress_all.57851796418559044160267210663095890482028144014035608391979303982758019766262
    Line 4991, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/17.lc_ctrl_stress_all/latest/run.log
```
  UVM_ERROR @ 2690859300 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 2690859300 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (lc_ctrl_errors_vseq.sv:762) [lc_ctrl_state_post_trans_vseq] Check failed state_error_act == state_error_exp (* [*] vs * [*]) has 1 failures:
- Test lc_ctrl_stress_all_with_rand_reset has 1 failures.
  - 22.lc_ctrl_stress_all_with_rand_reset.25603818133695245599803231502694291856199274602564860141598332851287068049904
    Line 5819, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/22.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 63823701129 ps: (lc_ctrl_errors_vseq.sv:762) [uvm_test_top.env.virtual_sequencer.lc_ctrl_state_post_trans_vseq] Check failed state_error_act == state_error_exp (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 63823701129 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:548) [lc_ctrl_common_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_state_error fired unexpectedly! has 1 failures:
- Test lc_ctrl_stress_all_with_rand_reset has 1 failures.
  - 32.lc_ctrl_stress_all_with_rand_reset.72148414353858694923535563638813875715524141184280173000250709321225776371968
    Line 38137, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/32.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 20976933404 ps: (cip_base_vseq.sv:548) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
  UVM_INFO @ 20976933404 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:594) [csr_utils::csr_spinwait] timeout lc_ctrl_reg_block.status.token_error (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=1) has 1 failures:
- Test lc_ctrl_volatile_unlock_smoke has 1 failures.
  - 42.lc_ctrl_volatile_unlock_smoke.48907988622831942635849616282008970035283188903273849500304738854904962003994
    Line 322, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/42.lc_ctrl_volatile_unlock_smoke/latest/run.log
```
  UVM_FATAL @ 138959951 ps: (csr_utils_pkg.sv:594) [csr_utils::csr_spinwait] timeout lc_ctrl_reg_block.status.token_error (addr=0x4d826904, Comparison=CompareOpEq, exp_data=0x1, call_count=1)
  UVM_INFO @ 138959951 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

LC_CTRL/VOLATILE_UNLOCK_DISABLED Simulation Results

Tuesday July 30 2024 23:02:08 UTC

GitHub Revision: fdfa12db04

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 101467584611478134588291649782725219255540557286164709436567235390830780957271

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `fdfa12db04`