LC_CTRL/VOLATILE_UNLOCK_DISABLED Simulation Results

Wednesday July 31 2024 23:02:38 UTC

GitHub Revision: e9b7e615a7

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 25204348267605859133056659113100703417171299070132656462514712657132693373848

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	7.970s	3.616ms	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.130s	14.033us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.150s	19.161us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	1.910s	260.790us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	1.510s	136.006us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	1.890s	116.058us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.150s	19.161us	20	20	100.00
		lc_ctrl_csr_aliasing	1.510s	136.006us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	9.810s	339.545us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	17.900s	1.255ms	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	0.900s	10.420us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	4.190s	356.309us	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	38.210s	1.049ms	50	50	100.00
V2	lc_errors	lc_ctrl_errors	23.460s	3.054ms	48	50	96.00
V2	security_escalation	lc_ctrl_state_failure	38.210s	1.049ms	50	50	100.00
		lc_ctrl_prog_failure	4.190s	356.309us	50	50	100.00
		lc_ctrl_errors	23.460s	3.054ms	48	50	96.00
		lc_ctrl_security_escalation	20.650s	3.547ms	50	50	100.00
		lc_ctrl_jtag_state_failure	2.046m	38.267ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	20.060s	1.452ms	20	20	100.00
		lc_ctrl_jtag_errors	2.315m	5.226ms	20	20	100.00
V2	jtag_access	lc_ctrl_jtag_smoke	11.050s	413.548us	20	20	100.00
		lc_ctrl_jtag_state_post_trans	33.300s	968.866us	20	20	100.00
		lc_ctrl_jtag_prog_failure	20.060s	1.452ms	20	20	100.00
		lc_ctrl_jtag_errors	2.315m	5.226ms	20	20	100.00
		lc_ctrl_jtag_access	26.140s	2.345ms	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	34.170s	1.146ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	4.890s	204.829us	10	10	100.00
		lc_ctrl_jtag_csr_rw	2.690s	90.554us	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	38.550s	6.211ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	22.840s	1.011ms	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	1.710s	129.558us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	5.600s	941.385us	10	10	100.00
		lc_ctrl_jtag_alert_test	2.510s	160.288us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	12.290s	1.638ms	10	10	100.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.120s	14.578us	50	50	100.00
V2	stress_all	lc_ctrl_stress_all	8.415m	68.756ms	50	50	100.00
V2	alert_test	lc_ctrl_alert_test	1.430s	31.808us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	4.710s	128.557us	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	4.710s	128.557us	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.130s	14.033us	5	5	100.00
		lc_ctrl_csr_rw	1.150s	19.161us	20	20	100.00
		lc_ctrl_csr_aliasing	1.510s	136.006us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.870s	39.503us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.130s	14.033us	5	5	100.00
		lc_ctrl_csr_rw	1.150s	19.161us	20	20	100.00
		lc_ctrl_csr_aliasing	1.510s	136.006us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.870s	39.503us	20	20	100.00
V2		TOTAL			698	700	99.71
V2S	tl_intg_err	lc_ctrl_sec_cm	40.350s	1.518ms	5	5	100.00
		lc_ctrl_tl_intg_err	4.340s	138.254us	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	4.340s	138.254us	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	17.900s	1.255ms	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	38.210s	1.049ms	50	50	100.00
		lc_ctrl_sec_cm	40.350s	1.518ms	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	38.210s	1.049ms	50	50	100.00
		lc_ctrl_sec_cm	40.350s	1.518ms	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	38.210s	1.049ms	50	50	100.00
		lc_ctrl_sec_cm	40.350s	1.518ms	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	38.210s	1.049ms	50	50	100.00
		lc_ctrl_sec_cm	40.350s	1.518ms	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	38.210s	1.049ms	50	50	100.00
		lc_ctrl_sec_cm	40.350s	1.518ms	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	38.210s	1.049ms	50	50	100.00
		lc_ctrl_sec_cm	40.350s	1.518ms	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	38.210s	1.049ms	50	50	100.00
		lc_ctrl_sec_cm	40.350s	1.518ms	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	38.210s	1.049ms	50	50	100.00
		lc_ctrl_sec_cm	40.350s	1.518ms	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	20.650s	3.547ms	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	9.810s	339.545us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	33.300s	968.866us	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	22.830s	523.051us	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	22.830s	523.051us	50	50	100.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	19.480s	1.904ms	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	21.620s	10.412ms	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	21.620s	10.412ms	50	50	100.00
V2S		TOTAL			175	175	100.00
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	1.592h	861.476ms	23	50	46.00
V3		TOTAL			23	50	46.00
		TOTAL			1001	1030	97.18

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	26	96.30
V2S	5	5	5	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.84	97.92	95.66	93.40	97.62	98.52	98.51	96.29

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:836) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 22 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 22 failures.

    • 0.lc_ctrl_stress_all_with_rand_reset.95736671703478372417196091572861300406611673107827191957787950304297261299351
      Line 329, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/0.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 5428688637 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 5428688637 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 1.lc_ctrl_stress_all_with_rand_reset.97966618065419979659853966547828147366446419303546122984499801907131749096719
      Line 34909, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/1.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 35770816348 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 35770816348 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 20 more failures.

• UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (* [*] vs * [*]) has 2 failures:

  • Test lc_ctrl_errors has 1 failures.

    • 6.lc_ctrl_errors.102683586070936799667688311358162132871519144752484122358865766974508129202374
      Line 4534, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/6.lc_ctrl_errors/latest/run.log

        UVM_ERROR @ 922462381 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 922462381 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 25.lc_ctrl_stress_all_with_rand_reset.56334735757322582588718798956445263890045415725597113755719173891815363165837
      Line 5075, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/25.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 6667142315 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 6667142315 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (lc_ctrl_errors_vseq.sv:769) [lc_ctrl_lc_errors_vseq] Check failed otp_error_act == otp_error_exp (* [*] vs * [*]) has 1 failures:

  • Test lc_ctrl_errors has 1 failures.

    • 11.lc_ctrl_errors.99498665544521883888037701588788570346475123901554041174168665587961549360028
      Line 3301, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/11.lc_ctrl_errors/latest/run.log

        UVM_ERROR @ 411112019 ps: (lc_ctrl_errors_vseq.sv:769) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed otp_error_act == otp_error_exp (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 411112019 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:548) [lc_ctrl_common_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_state_error fired unexpectedly! has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 14.lc_ctrl_stress_all_with_rand_reset.94334416068295062603463814793836586939942278765327635729061628739967425864901
      Line 58872, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/14.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 32523047153 ps: (cip_base_vseq.sv:548) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
        UVM_INFO @ 32523047153 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:548) [lc_ctrl_regwen_during_op_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_prog_error fired unexpectedly! has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 36.lc_ctrl_stress_all_with_rand_reset.94905895859726739217467195678871677482331818227880711559560970845574492676078
      Line 11776, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/36.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 5796582397 ps: (cip_base_vseq.sv:548) [uvm_test_top.env.virtual_sequencer.lc_ctrl_regwen_during_op_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_prog_error fired unexpectedly!
        UVM_INFO @ 5796582397 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Error-[CNST-STOF] Constraint solver timeout failure has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 41.lc_ctrl_stress_all_with_rand_reset.72442963045249657464366709165917555416629264128504324189924392023087264520816
      Line 47470, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/41.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        Error-[CNST-STOF] Constraint solver timeout failure
        ../src/lowrisc_dv_sec_cm_0/prim_sparse_fsm_flop_if.sv, 43
          Exceeded cpu time limit during solve.
          Please use the run-time switch +ntb_solver_cpu_limit to increase the cpu
          limit.  The default cpu limit is 1000 seconds per partition.
      

• UVM_ERROR (cip_base_scoreboard.sv:301) scoreboard [scoreboard] alert fatal_prog_error did not trigger max_delay:* has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 45.lc_ctrl_stress_all_with_rand_reset.66424150862140392165596502418589725118067227093183162443767474137812000234882
      Line 4708, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/45.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 2987859575 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 2987859575 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

• Latest
• 2024.07.31_09.04.51
• 2024.07.30_09.22.27
• 2024.07.29_07.47.22
• 2024.07.28_10.45.56
• 2024.07.27_09.37.44
• 2024.07.26_09.01.02
• 2024.07.25_08.31.54