LC_CTRL/VOLATILE_UNLOCK_DISABLED Simulation Results

Thursday August 01 2024 23:02:20 UTC

GitHub Revision: 625f353e9c

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 85273092133191575795496895645039765542965103003083525273509664765586668778052

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	17.330s	305.349us	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.210s	15.290us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.020s	43.433us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	2.360s	90.948us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	1.740s	166.758us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	2.430s	32.844us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.020s	43.433us	20	20	100.00
		lc_ctrl_csr_aliasing	1.740s	166.758us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	9.860s	535.061us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	22.530s	778.287us	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	1.040s	88.853us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	5.000s	218.601us	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	35.250s	345.657us	50	50	100.00
V2	lc_errors	lc_ctrl_errors	20.760s	489.616us	50	50	100.00
V2	security_escalation	lc_ctrl_state_failure	35.250s	345.657us	50	50	100.00
		lc_ctrl_prog_failure	5.000s	218.601us	50	50	100.00
		lc_ctrl_errors	20.760s	489.616us	50	50	100.00
		lc_ctrl_security_escalation	14.770s	928.881us	50	50	100.00
		lc_ctrl_jtag_state_failure	1.980m	11.364ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	15.660s	3.870ms	20	20	100.00
		lc_ctrl_jtag_errors	2.204m	19.748ms	20	20	100.00
V2	jtag_access	lc_ctrl_jtag_smoke	13.870s	2.087ms	20	20	100.00
		lc_ctrl_jtag_state_post_trans	35.080s	6.477ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	15.660s	3.870ms	20	20	100.00
		lc_ctrl_jtag_errors	2.204m	19.748ms	20	20	100.00
		lc_ctrl_jtag_access	26.060s	9.960ms	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	31.140s	4.359ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	3.150s	95.639us	10	10	100.00
		lc_ctrl_jtag_csr_rw	3.680s	132.210us	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	56.260s	10.601ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	20.800s	4.187ms	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	1.510s	33.971us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	7.280s	531.665us	10	10	100.00
		lc_ctrl_jtag_alert_test	2.610s	355.237us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	1.703m	17.526ms	9	10	90.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.460s	47.764us	49	50	98.00
V2	stress_all	lc_ctrl_stress_all	8.895m	71.083ms	50	50	100.00
V2	alert_test	lc_ctrl_alert_test	1.310s	22.861us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	4.740s	126.077us	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	4.740s	126.077us	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.210s	15.290us	5	5	100.00
		lc_ctrl_csr_rw	1.020s	43.433us	20	20	100.00
		lc_ctrl_csr_aliasing	1.740s	166.758us	5	5	100.00
		lc_ctrl_same_csr_outstanding	2.050s	48.717us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.210s	15.290us	5	5	100.00
		lc_ctrl_csr_rw	1.020s	43.433us	20	20	100.00
		lc_ctrl_csr_aliasing	1.740s	166.758us	5	5	100.00
		lc_ctrl_same_csr_outstanding	2.050s	48.717us	20	20	100.00
V2		TOTAL			698	700	99.71
V2S	tl_intg_err	lc_ctrl_sec_cm	36.900s	218.407us	5	5	100.00
		lc_ctrl_tl_intg_err	4.210s	109.009us	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	4.210s	109.009us	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	22.530s	778.287us	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	35.250s	345.657us	50	50	100.00
		lc_ctrl_sec_cm	36.900s	218.407us	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	35.250s	345.657us	50	50	100.00
		lc_ctrl_sec_cm	36.900s	218.407us	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	35.250s	345.657us	50	50	100.00
		lc_ctrl_sec_cm	36.900s	218.407us	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	35.250s	345.657us	50	50	100.00
		lc_ctrl_sec_cm	36.900s	218.407us	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	35.250s	345.657us	50	50	100.00
		lc_ctrl_sec_cm	36.900s	218.407us	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	35.250s	345.657us	50	50	100.00
		lc_ctrl_sec_cm	36.900s	218.407us	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	35.250s	345.657us	50	50	100.00
		lc_ctrl_sec_cm	36.900s	218.407us	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	35.250s	345.657us	50	50	100.00
		lc_ctrl_sec_cm	36.900s	218.407us	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	14.770s	928.881us	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	9.860s	535.061us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	35.080s	6.477ms	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	17.890s	722.155us	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	17.890s	722.155us	50	50	100.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	27.120s	2.233ms	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	22.790s	3.036ms	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	22.790s	3.036ms	50	50	100.00
V2S		TOTAL			175	175	100.00
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	59.852m	42.147ms	25	50	50.00
V3		TOTAL			25	50	50.00
		TOTAL			1003	1030	97.38

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	25	92.59
V2S	5	5	5	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.53	97.92	95.84	93.40	95.24	98.52	98.51	96.29

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:836) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 21 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 21 failures.

    • 0.lc_ctrl_stress_all_with_rand_reset.76637929487545039335408376335558495489524291507795170805077863113265476841524
      Line 7058, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/0.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1429443626 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 1429443626 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 1.lc_ctrl_stress_all_with_rand_reset.51520079587855533824406464161972569630401701082832676472834899313445067892263
      Line 9771, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/1.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 5117915916 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 5117915916 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 19 more failures.

• UVM_FATAL (lc_ctrl_jtag_priority_vseq.sv:113) [lc_ctrl_jtag_priority_vseq] timeout occurred! has 1 failures:

  • Test lc_ctrl_jtag_priority has 1 failures.

    • 3.lc_ctrl_jtag_priority.61748162540807260527107133141320410785597869638947209643392986355893713265149
      Line 597, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/3.lc_ctrl_jtag_priority/latest/run.log

        UVM_FATAL @ 10008303260 ps: (lc_ctrl_jtag_priority_vseq.sv:113) [uvm_test_top.env.virtual_sequencer.lc_ctrl_jtag_priority_vseq] timeout occurred!
        UVM_INFO @ 10008303260 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (csr_utils_pkg.sv:594) [csr_utils::csr_spinwait] timeout lc_ctrl_reg_block.status.token_error (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=1) has 1 failures:

  • Test lc_ctrl_volatile_unlock_smoke has 1 failures.

    • 5.lc_ctrl_volatile_unlock_smoke.106455701837320808470461087027726809329783065077802658932588937101382093437919
      Line 322, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/5.lc_ctrl_volatile_unlock_smoke/latest/run.log

        UVM_FATAL @ 122499943 ps: (csr_utils_pkg.sv:594) [csr_utils::csr_spinwait] timeout lc_ctrl_reg_block.status.token_error (addr=0xf928fd04, Comparison=CompareOpEq, exp_data=0x1, call_count=1)
        UVM_INFO @ 122499943 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_scoreboard.sv:301) scoreboard [scoreboard] alert fatal_prog_error did not trigger max_delay:* has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 12.lc_ctrl_stress_all_with_rand_reset.43292613976760572604936744848628723378259211447241913688769644859368235202995
      Line 70008, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/12.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 183437070170 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 183437070170 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:548) [lc_ctrl_common_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_state_error fired unexpectedly! has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 30.lc_ctrl_stress_all_with_rand_reset.32657426361191230863048795893637681463441160445256178610440556553637555028437
      Line 40106, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/30.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 44702212148 ps: (cip_base_vseq.sv:548) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
        UVM_INFO @ 44702212148 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:548) [lc_ctrl_smoke_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_prog_error fired unexpectedly! has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 38.lc_ctrl_stress_all_with_rand_reset.5467618833676181712488507256871874854283434226623928891830954847220008398529
      Line 6130, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/38.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 2029356336 ps: (cip_base_vseq.sv:548) [uvm_test_top.env.virtual_sequencer.lc_ctrl_smoke_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_prog_error fired unexpectedly!
        UVM_INFO @ 2029356336 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Job lc_ctrl_volatile_unlock_disabled-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 49.lc_ctrl_stress_all_with_rand_reset.45622331747876406243629608382425177150744559180544810484161335003135200422663
      Log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/49.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        Job ID: smart:90bffb99-91a8-4ffe-b519-eb028261b5ff
      

Past Results

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• 2024.08.01_09.35.26
• 2024.07.31_09.04.51
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