LC_CTRL/VOLATILE_UNLOCK_DISABLED Simulation Results

Friday August 02 2024 23:02:48 UTC

GitHub Revision: c8985d6745

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 75989420798843487383163268541581889763599806834398027919895759109584083292465

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	8.620s	560.569us	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.290s	74.343us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.110s	27.808us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	3.100s	91.778us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	1.640s	63.368us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	2.060s	26.511us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.110s	27.808us	20	20	100.00
		lc_ctrl_csr_aliasing	1.640s	63.368us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	11.450s	360.631us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	22.930s	3.787ms	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	0.930s	38.067us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	6.340s	632.318us	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	35.270s	1.192ms	50	50	100.00
V2	lc_errors	lc_ctrl_errors	22.570s	3.753ms	50	50	100.00
V2	security_escalation	lc_ctrl_state_failure	35.270s	1.192ms	50	50	100.00
		lc_ctrl_prog_failure	6.340s	632.318us	50	50	100.00
		lc_ctrl_errors	22.570s	3.753ms	50	50	100.00
		lc_ctrl_security_escalation	20.310s	2.224ms	50	50	100.00
		lc_ctrl_jtag_state_failure	1.700m	3.127ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	14.220s	2.179ms	20	20	100.00
		lc_ctrl_jtag_errors	1.462m	3.215ms	20	20	100.00
V2	jtag_access	lc_ctrl_jtag_smoke	10.880s	391.208us	20	20	100.00
		lc_ctrl_jtag_state_post_trans	28.930s	3.469ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	14.220s	2.179ms	20	20	100.00
		lc_ctrl_jtag_errors	1.462m	3.215ms	20	20	100.00
		lc_ctrl_jtag_access	22.470s	2.596ms	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	36.860s	7.407ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	2.730s	81.092us	10	10	100.00
		lc_ctrl_jtag_csr_rw	2.610s	1.572ms	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	21.060s	4.849ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	12.510s	1.090ms	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	1.430s	22.555us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	6.440s	917.554us	10	10	100.00
		lc_ctrl_jtag_alert_test	2.070s	56.838us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	48.540s	10.011ms	9	10	90.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.230s	15.905us	50	50	100.00
V2	stress_all	lc_ctrl_stress_all	10.277m	18.378ms	48	50	96.00
V2	alert_test	lc_ctrl_alert_test	1.350s	29.356us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	5.240s	281.142us	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	5.240s	281.142us	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.290s	74.343us	5	5	100.00
		lc_ctrl_csr_rw	1.110s	27.808us	20	20	100.00
		lc_ctrl_csr_aliasing	1.640s	63.368us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.900s	186.765us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.290s	74.343us	5	5	100.00
		lc_ctrl_csr_rw	1.110s	27.808us	20	20	100.00
		lc_ctrl_csr_aliasing	1.640s	63.368us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.900s	186.765us	20	20	100.00
V2		TOTAL			697	700	99.57
V2S	tl_intg_err	lc_ctrl_sec_cm	41.180s	358.784us	5	5	100.00
		lc_ctrl_tl_intg_err	4.860s	688.409us	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	4.860s	688.409us	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	22.930s	3.787ms	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	35.270s	1.192ms	50	50	100.00
		lc_ctrl_sec_cm	41.180s	358.784us	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	35.270s	1.192ms	50	50	100.00
		lc_ctrl_sec_cm	41.180s	358.784us	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	35.270s	1.192ms	50	50	100.00
		lc_ctrl_sec_cm	41.180s	358.784us	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	35.270s	1.192ms	50	50	100.00
		lc_ctrl_sec_cm	41.180s	358.784us	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	35.270s	1.192ms	50	50	100.00
		lc_ctrl_sec_cm	41.180s	358.784us	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	35.270s	1.192ms	50	50	100.00
		lc_ctrl_sec_cm	41.180s	358.784us	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	35.270s	1.192ms	50	50	100.00
		lc_ctrl_sec_cm	41.180s	358.784us	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	35.270s	1.192ms	50	50	100.00
		lc_ctrl_sec_cm	41.180s	358.784us	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	20.310s	2.224ms	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	11.450s	360.631us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	28.930s	3.469ms	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	18.400s	823.258us	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	18.400s	823.258us	50	50	100.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	20.650s	2.266ms	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	16.860s	4.506ms	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	16.860s	4.506ms	50	50	100.00
V2S		TOTAL			175	175	100.00
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	2.255h	51.007ms	27	50	54.00
V3		TOTAL			27	50	54.00
		TOTAL			1004	1030	97.48

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	25	92.59
V2S	5	5	5	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.79	97.92	95.66	93.40	97.62	98.52	98.51	95.94

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:836) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 17 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 17 failures.

    • 4.lc_ctrl_stress_all_with_rand_reset.51182449508625559761128231766208286935770662702187398498064808123987827062720
      Line 5658, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/4.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 10283227807 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 10283227807 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 5.lc_ctrl_stress_all_with_rand_reset.84930417072472653603519052108862115457195774313283779036600394411675508647536
      Line 37489, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/5.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 31226254760 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 31226254760 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 15 more failures.

• Error-[CNST-STOF] Constraint solver timeout failure has 4 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 4 failures.

    • 17.lc_ctrl_stress_all_with_rand_reset.59630345766873591032991126014884499695441723761706547219619433998247387683876
      Line 48942, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/17.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        Error-[CNST-STOF] Constraint solver timeout failure
        ../src/lowrisc_dv_sec_cm_0/prim_sparse_fsm_flop_if.sv, 43
          Exceeded cpu time limit during solve.
          Please use the run-time switch +ntb_solver_cpu_limit to increase the cpu
          limit.  The default cpu limit is 1000 seconds per partition.
      

    • 25.lc_ctrl_stress_all_with_rand_reset.17072620125675409076987457056669871746377475016343971277491163277857800773187
      Line 41947, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/25.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        Error-[CNST-STOF] Constraint solver timeout failure
        ../src/lowrisc_dv_sec_cm_0/prim_sparse_fsm_flop_if.sv, 43
          Exceeded cpu time limit during solve.
          Please use the run-time switch +ntb_solver_cpu_limit to increase the cpu
          limit.  The default cpu limit is 1000 seconds per partition.
      

    • ... and 2 more failures.

• UVM_ERROR (cip_base_vseq.sv:548) [lc_ctrl_common_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_state_error fired unexpectedly! has 2 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 2 failures.

    • 11.lc_ctrl_stress_all_with_rand_reset.105328070900149271327648291503639211110531556846501855610384126633612648823390
      Line 37034, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/11.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 93912600092 ps: (cip_base_vseq.sv:548) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
        UVM_INFO @ 93912600092 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 30.lc_ctrl_stress_all_with_rand_reset.37815383664919006424866761532087316540719393010089426159834949728096657748958
      Line 18655, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/30.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 64757204431 ps: (cip_base_vseq.sv:548) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
        UVM_INFO @ 64757204431 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (lc_ctrl_jtag_priority_vseq.sv:113) [lc_ctrl_jtag_priority_vseq] timeout occurred! has 1 failures:

  • Test lc_ctrl_jtag_priority has 1 failures.

    • 5.lc_ctrl_jtag_priority.113428236430683733020876059095862706910255464203586564878621547826931440797762
      Line 648, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/5.lc_ctrl_jtag_priority/latest/run.log

        UVM_FATAL @ 10011014038 ps: (lc_ctrl_jtag_priority_vseq.sv:113) [uvm_test_top.env.virtual_sequencer.lc_ctrl_jtag_priority_vseq] timeout occurred!
        UVM_INFO @ 10011014038 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (* [*] vs * [*]) has 1 failures:

  • Test lc_ctrl_stress_all has 1 failures.

    • 29.lc_ctrl_stress_all.101599182174550991012473076004112854159391924144047710207730306123299144295449
      Line 10306, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/29.lc_ctrl_stress_all/latest/run.log

        UVM_ERROR @ 6088987364 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 6088987364 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_scoreboard.sv:301) scoreboard [scoreboard] alert fatal_prog_error did not trigger max_delay:* has 1 failures:

  • Test lc_ctrl_stress_all has 1 failures.

    • 42.lc_ctrl_stress_all.103232858117828223859025288110339418120149399086792129007455426601151839759890
      Line 11802, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/42.lc_ctrl_stress_all/latest/run.log

        UVM_ERROR @ 3992324163 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 3992324163 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

• Latest
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• 2024.07.31_09.04.51
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